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From: Jason Gunthorpe <jgg@nvidia.com>
To: "Suthikulpanit, Suravee" <suravee.suthikulpanit@amd.com>
Cc: linux-kernel@vger.kernel.org, iommu@lists.linux.dev,
	joro@8bytes.org, robin.murphy@arm.com, vasant.hegde@amd.com,
	kevin.tian@intel.com, jon.grimm@amd.com, santosh.shukla@amd.com,
	pandoh@google.com, kumaranand@google.com
Subject: Re: [PATCH v4 3/6] iommu/amd: Modify set_dte_entry() to use 256-bit DTE helpers
Date: Thu, 3 Oct 2024 15:49:31 -0300	[thread overview]
Message-ID: <20241003184931.GC1365916@nvidia.com> (raw)
In-Reply-To: <aaaab5d3-047c-4d48-a4d9-cb5b4adc733c@amd.com>

On Thu, Oct 03, 2024 at 11:16:19PM +0700, Suthikulpanit, Suravee wrote:

> > > +	tmp = gcr3_info->glx;
> > > +	target->data[0] |= (tmp & DTE_GLX_MASK) << DTE_GLX_SHIFT;
> > > +	if (pdom_is_v2_pgtbl_mode(dev_data->domain))
> > > +		target->data[0] |= DTE_FLAG_GIOV;
> > 
> > When does this get called to install a gcr3 table without a v2 domain?
> 
> The GCR3 table is also used when we setup v2 table for SVA stuff. In such
> case, we would be setting up w/ PASID. Therefore, the GIOV bit is not
> needed.

If I understand the manual right this should be written as:

if (dev_data->domain->type != IDENTITY)
   target->data[0] |= DTE_FLAG_GIOV;

Ie everything on the RID except identity should be translated through
PASID 0 and if PASID 0 is a V2 page table then it will translate and
if PASID 0 is non-valid then it will block?

Identity needs to not use GIOV otherwise it will be blocking?

Jason

  reply	other threads:[~2024-10-03 18:49 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-09-16 17:17 [PATCH v4 0/6] iommu/amd: Use 128-bit cmpxchg operation to update DTE Suravee Suthikulpanit
2024-09-16 17:18 ` [PATCH v4 1/6] iommu/amd: Disable AMD IOMMU if CMPXCHG16B feature is not supported Suravee Suthikulpanit
2024-09-16 17:18 ` [PATCH v4 2/6] iommu/amd: Introduce helper function to update 256-bit DTE Suravee Suthikulpanit
2024-09-26 19:46   ` Jason Gunthorpe
2024-10-03 16:15     ` Suthikulpanit, Suravee
2024-10-03 18:54       ` Jason Gunthorpe
2024-09-16 17:18 ` [PATCH v4 3/6] iommu/amd: Modify set_dte_entry() to use 256-bit DTE helpers Suravee Suthikulpanit
2024-09-26 19:56   ` Jason Gunthorpe
2024-10-03 16:16     ` Suthikulpanit, Suravee
2024-10-03 18:49       ` Jason Gunthorpe [this message]
2024-09-16 17:18 ` [PATCH v4 4/6] iommu/amd: Introduce helper function get_dte256() Suravee Suthikulpanit
2024-09-26 19:49   ` Jason Gunthorpe
2024-09-16 17:18 ` [PATCH v4 5/6] iommu/amd: Modify clear_dte_entry() to avoid in-place update Suravee Suthikulpanit
2024-09-26 19:54   ` Jason Gunthorpe
2024-10-03 16:15     ` Suthikulpanit, Suravee
2024-09-16 17:18 ` [PATCH v4 6/6] iommu/amd: Lock DTE before updating the entry with WRITE_ONCE() Suravee Suthikulpanit
2024-09-26 19:58   ` Jason Gunthorpe
2024-09-23 15:03 ` [PATCH v4 0/6] iommu/amd: Use 128-bit cmpxchg operation to update DTE Suthikulpanit, Suravee

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