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From: Mark Brown <broonie@kernel.org>
To: Catalin Marinas <catalin.marinas@arm.com>,
	 Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
	 Oliver Upton <oliver.upton@linux.dev>,
	Joey Gouly <joey.gouly@arm.com>,
	 Suzuki K Poulose <suzuki.poulose@arm.com>,
	Shuah Khan <shuah@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org,
	 kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org,
	 linux-kernel@vger.kernel.org, Mark Brown <broonie@kernel.org>
Subject: [PATCH v14 4/5] KVM: arm64: Set PSTATE.EXLOCK when entering an exception
Date: Sat, 05 Oct 2024 11:37:31 +0100	[thread overview]
Message-ID: <20241005-arm64-gcs-v14-4-59060cd6092b@kernel.org> (raw)
In-Reply-To: <20241005-arm64-gcs-v14-0-59060cd6092b@kernel.org>

As per DDI 0487 RWTXBY we need to manage PSTATE.EXLOCK when entering an
exception, when the exception is entered from a lower EL the bit is cleared
while if entering from the same EL it is set to GCSCR_ELx.EXLOCKEN.
Implement this behaviour in enter_exception64().

Signed-off-by: Mark Brown <broonie@kernel.org>
---
 arch/arm64/include/uapi/asm/ptrace.h |  2 ++
 arch/arm64/kvm/hyp/exception.c       | 10 ++++++++++
 2 files changed, 12 insertions(+)

diff --git a/arch/arm64/include/uapi/asm/ptrace.h b/arch/arm64/include/uapi/asm/ptrace.h
index 0f39ba4f3efd4a8760f0fca0fbf1a2563b191c7d..9987957f4f7137bf107653b817885bb976853a83 100644
--- a/arch/arm64/include/uapi/asm/ptrace.h
+++ b/arch/arm64/include/uapi/asm/ptrace.h
@@ -37,6 +37,7 @@
 #define PSR_MODE_EL3t	0x0000000c
 #define PSR_MODE_EL3h	0x0000000d
 #define PSR_MODE_MASK	0x0000000f
+#define PSR_EL_MASK	0x0000000c
 
 /* AArch32 CPSR bits */
 #define PSR_MODE32_BIT		0x00000010
@@ -56,6 +57,7 @@
 #define PSR_C_BIT	0x20000000
 #define PSR_Z_BIT	0x40000000
 #define PSR_N_BIT	0x80000000
+#define PSR_EXLOCK_BIT 0x400000000
 
 #define PSR_BTYPE_SHIFT		10
 
diff --git a/arch/arm64/kvm/hyp/exception.c b/arch/arm64/kvm/hyp/exception.c
index 424a5107cddb5e1cdd75ef3581adef03aaadabb7..0d41b9b75cf83250b2c0d20cd82c153869efb0e4 100644
--- a/arch/arm64/kvm/hyp/exception.c
+++ b/arch/arm64/kvm/hyp/exception.c
@@ -160,6 +160,16 @@ static void enter_exception64(struct kvm_vcpu *vcpu, unsigned long target_mode,
 	// PSTATE.BTYPE is set to zero upon any exception to AArch64
 	// See ARM DDI 0487E.a, pages D1-2293 to D1-2294.
 
+	// PSTATE.EXLOCK is set to 0 upon any exception to a higher
+	// EL, or to GCSCR_ELx.EXLOCKEN for an exception to the same
+	// exception level.  See ARM DDI 0487 RWTXBY, D.1.3.2 in K.a.
+	if (kvm_has_gcs(vcpu->kvm) &&
+	    (target_mode & PSR_EL_MASK) == (mode & PSR_EL_MASK)) {
+		u64 gcscr = __vcpu_read_sys_reg(vcpu, GCSCR_EL1);
+		if (gcscr & GCSCR_ELx_EXLOCKEN)
+			new |= PSR_EXLOCK_BIT;
+	}
+
 	new |= PSR_D_BIT;
 	new |= PSR_A_BIT;
 	new |= PSR_I_BIT;

-- 
2.39.2


  parent reply	other threads:[~2024-10-05 10:37 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-10-05 10:37 [PATCH v14 0/5] KVM: arm64: Provide guest support for GCS Mark Brown
2024-10-05 10:37 ` [PATCH v14 1/5] KVM: arm64: Expose S1PIE to guests Mark Brown
2024-10-05 10:37 ` [PATCH v14 2/5] arm64/gcs: Ensure FGTs for EL1 GCS instructions are disabled Mark Brown
2024-10-05 10:37 ` [PATCH v14 3/5] KVM: arm64: Manage GCS access and registers for guests Mark Brown
2024-10-05 11:34   ` Marc Zyngier
2024-10-05 13:08     ` Mark Brown
2024-10-05 13:18       ` Marc Zyngier
2024-10-05 13:48         ` Mark Brown
2024-10-05 14:02           ` Marc Zyngier
2024-10-05 14:26             ` Mark Brown
2024-10-05 14:33               ` Marc Zyngier
2024-10-05 10:37 ` Mark Brown [this message]
2024-10-05 12:36   ` [PATCH v14 4/5] KVM: arm64: Set PSTATE.EXLOCK when entering an exception Marc Zyngier
2024-10-05 14:14     ` Mark Brown
2024-10-05 16:35       ` Marc Zyngier
2024-10-05 10:37 ` [PATCH v14 5/5] KVM: selftests: arm64: Add GCS registers to get-reg-list Mark Brown

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