From: Christoph Hellwig <hch@lst.de>
To: Tero Kristo <tero.kristo@linux.intel.com>
Cc: Christoph Hellwig <hch@lst.de>,
linux-kernel@vger.kernel.org, axboe@kernel.dk,
linux-nvme@lists.infradead.org, sagi@grimberg.me,
kbusch@kernel.org
Subject: Re: [PATCH 1/1] nvme-pci: Add CPU latency pm-qos handling
Date: Wed, 9 Oct 2024 10:00:52 +0200 [thread overview]
Message-ID: <20241009080052.GA16711@lst.de> (raw)
In-Reply-To: <913b063d0638614bc95d92969879d2096ffc0722.camel@linux.intel.com>
On Wed, Oct 09, 2024 at 09:45:07AM +0300, Tero Kristo wrote:
> Initially, I posted the patch against block layer, but there the
> recommendation was to move this closer to the HW; i.e. NVMe driver
> level.
Even if it is called from NVMe, at lot of the code is not nvme specific.
Some of it appears block specific and other pats are entirely generic.
But I still don't see how walking cpumasks and updating paramters in
far away (in terms of cache lines and pointer dereferences) for every
single I/O could work without having a huge performance impact.
next prev parent reply other threads:[~2024-10-09 8:00 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-04 10:09 [PATCH 0/1] nvme-pci: Add CPU latency pm-qos handling Tero Kristo
2024-10-04 10:09 ` [PATCH 1/1] " Tero Kristo
2024-10-07 6:19 ` Christoph Hellwig
2024-10-09 6:45 ` Tero Kristo
2024-10-09 8:00 ` Christoph Hellwig [this message]
2024-10-09 8:24 ` Tero Kristo
2024-10-15 9:25 ` Tero Kristo
2024-10-15 13:29 ` Christoph Hellwig
2024-10-18 7:58 ` Tero Kristo
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