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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?kvB92V/WAghF7r2JfqdAVEq/CPFf9G4bEYjygDodMLbyWk5d/aQKtQXc2mCx?= =?us-ascii?Q?NwIxivoY3RORv5/TdU0Amb7ULvR1CU7rQRSIo2qdkG9hpU1RS9jnCORS51kO?= =?us-ascii?Q?pYFwOV40LpvvE3Zl0I43esYJC+FqMZi1EPdnCap/qdeNgmwjDEOxbkPxxnj4?= =?us-ascii?Q?j5IkLCutmINVvsBYYUx/WkLTtKHHBisSUGgSnsKspmCg731vxhiImaWd04sO?= =?us-ascii?Q?cJ+bFPU+VFDfDuQdV8fgDwTodnnS/oKBMzrUSRDNGQtADHKrOMAG2dmtUKjS?= =?us-ascii?Q?hcGjN8PurSQzDThqCzBg17ciTISmrLe3rx8h1mCqBmchsPrbx+rUdZgc7Su5?= =?us-ascii?Q?YNIifuAg1+K20Md1j3JRITyJC2s0Ux328OzilnU2Mob2SuVJGN8vQpUSL6pY?= =?us-ascii?Q?0ZsqEA2CaX8o2YzkSH7MptSpeytDN/fHjGGAXKRN5G5d7jLEx5VifHrSiQRR?= =?us-ascii?Q?WgNwPbSGcUO7IyfE9TKybNCeu7alxH2ZRCqUwCb4Us/9l/YqerWHkS6a8NCv?= =?us-ascii?Q?chhQ2g87oGZxvzNoF0eIY7NY1ZwSsBezrg8X4CVs3ckLgX/j4L6w3xKjvQe/?= =?us-ascii?Q?QLvj6EGZKUSMlVIn1NukW1EECQ6wEgSrlK/ECaB50WqBGWLzXVwLcnov7aLi?= =?us-ascii?Q?J61Vyjg6KvLDKr8Gt9VkZiXXKLZull8z0CW5Lx11+xxebYYXJjfJfd9o6KIz?= =?us-ascii?Q?PvDPAUKqHxagVfZw06cX0vY+fj9IxifViNs+KUR/RE1kL8GlASfL0WGeLj9C?= =?us-ascii?Q?I/EEL/HxDC1wvq5srqSFrW/cd2IR0urvznpYDlyexbjqDS4pWtSCfW+mKoXj?= =?us-ascii?Q?5c1m2UJny4rXdz3Lvz0q0Kt7xVmmXoaxPQGF4XGF7iGmAFQsxDC73t9aC3K6?= =?us-ascii?Q?mP5dPEdKlpoUeqhWANQ2mnDj/RQarv7McCwfgQ6G9Yhj1HCwNGkdsr+YRcfP?= =?us-ascii?Q?RaQee7ULn14+l1BtHW1Y/NiREjhK2cnDn/gZSZfKLuIjg1R5N2jcvZx9xUl8?= =?us-ascii?Q?svSJB3PT5reWQkW3ON3qsekYaYclcE59fZtTdS6U3A6r8S76FPOmd1N77hx6?= =?us-ascii?Q?0QKwElAO2wX0LKT79NGc4Wo8r+U67UIydCtVS7ehRe9opEv1KRwCPJoxl2AB?= =?us-ascii?Q?+X45gjVjVCwLvnc2Z0jHmiuXDnpt4SwbCQcVmIgGtqz9xQG+CX3Vez86ufg0?= =?us-ascii?Q?HYvo/Ji6I6oEJK0kHVc2OrTeCipEwAUgytgR7ICHIPjof0Cwtf4DN5o1pbzj?= =?us-ascii?Q?V60K9xrGycT//RnLBH5bUoeVarhZq6V7supjPughv6mfW+qlmNTmxIgPkE+5?= =?us-ascii?Q?j1a0aVd2R1UlvS6K2aaz3uWSGUD+vB1z/hYQBYYoa/U9w0fMc3if7Mz5gUiB?= =?us-ascii?Q?IlAflC0/do0OIMYNvDAUklNmc+okR6sov+opX9k9EK6zIXa2rufl4IlD+Y60?= =?us-ascii?Q?sT/gRZwdvbKOy5Spx/TRbmHtKAQ8YvlGWI73EhaNnFQwCbuSs+Ys6Kf7RbQJ?= =?us-ascii?Q?1NQpnIYM0+3RrpQ0UjUgyjCta2MlD/g57gBHIVsqxSp/8OvkjCPk6YhwrSng?= =?us-ascii?Q?pDZ5l3aQ1DRV322BJyM=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 88352b1e-5b11-4423-5922-08dcede9c8b5 X-MS-Exchange-CrossTenant-AuthSource: CH3PR12MB8659.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2024 13:52:33.1714 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 2OG0f0MnzTuYkU2OkWDXQ1Nt1WqN3mdei0KEB0ATAhEXajSVRIIwr7Czv4VEJXeB X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB8439 On Wed, Oct 16, 2024 at 05:17:52AM +0000, Suravee Suthikulpanit wrote: > +static void set_dte_gcr3_table(struct amd_iommu *iommu, > + struct iommu_dev_data *dev_data, > + struct dev_table_entry *target) > +{ > + struct gcr3_tbl_info *gcr3_info = &dev_data->gcr3_info; > + u64 tmp, gcr3; > + > + if (!gcr3_info->gcr3_tbl) > + return; > + > + pr_debug("%s: devid=%#x, glx=%#x, gcr3_tbl=%#llx\n", > + __func__, dev_data->devid, gcr3_info->glx, > + (unsigned long long)gcr3_info->gcr3_tbl); > + > + tmp = gcr3_info->glx; > + target->data[0] |= (tmp & DTE_GLX_MASK) << DTE_GLX_SHIFT; > + if (pdom_is_v2_pgtbl_mode(dev_data->domain)) > + target->data[0] |= DTE_FLAG_GIOV; > + target->data[0] |= DTE_FLAG_GV; > + > + > + gcr3 = iommu_virt_to_phys(gcr3_info->gcr3_tbl); > + > + /* Encode GCR3 table into DTE */ > + tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A; > + target->data[0] |= tmp; > + tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B; > + tmp |= DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C; > + target->data[1] |= tmp; > + > + /* Guest page table can only support 4 and 5 levels */ > + if (amd_iommu_gpt_level == PAGE_MODE_5_LEVEL) > + target->data[2] |= ((u64)GUEST_PGTABLE_5_LEVEL << DTE_GPT_LEVEL_SHIFT); > +} This looks OK but suggest to use the new macros and things, it is much more readable: diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h index 53e129835b2668..fbae0803bceaa0 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -409,8 +409,7 @@ #define DTE_FLAG_HAD (3ULL << 7) #define DTE_FLAG_GIOV BIT_ULL(54) #define DTE_FLAG_GV BIT_ULL(55) -#define DTE_GLX_SHIFT (56) -#define DTE_GLX_MASK (3) +#define DTE_GLX GENMASK_ULL(57, 56) #define DTE_FLAG_IR BIT_ULL(61) #define DTE_FLAG_IW BIT_ULL(62) @@ -418,15 +417,10 @@ #define DTE_FLAG_MASK (0x3ffULL << 32) #define DEV_DOMID_MASK 0xffffULL -#define DTE_GCR3_VAL_A(x) (((x) >> 12) & 0x00007ULL) -#define DTE_GCR3_VAL_B(x) (((x) >> 15) & 0x0ffffULL) -#define DTE_GCR3_VAL_C(x) (((x) >> 31) & 0x1fffffULL) +#define DTE_GCR3_14_12 GENMASK_ULL(57, 56) +#define DTE_GCR3_30_15 GENMASK_ULL(31, 16) +#define DTE_GCR3_51_31 GENMASK_ULL(63, 43) -#define DTE_GCR3_SHIFT_A 58 -#define DTE_GCR3_SHIFT_B 16 -#define DTE_GCR3_SHIFT_C 43 - -#define DTE_GPT_LEVEL_SHIFT 54 #define DTE_GPT_LEVEL_MASK GENMASK_ULL(55, 54) #define GCR3_VALID 0x01ULL diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index caea101df7b93d..b0d2174583dbc9 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -2012,7 +2012,7 @@ static void set_dte_gcr3_table(struct amd_iommu *iommu, struct dev_table_entry *target) { struct gcr3_tbl_info *gcr3_info = &dev_data->gcr3_info; - u64 tmp, gcr3; + u64 gcr3; if (!gcr3_info->gcr3_tbl) return; @@ -2021,25 +2021,24 @@ static void set_dte_gcr3_table(struct amd_iommu *iommu, __func__, dev_data->devid, gcr3_info->glx, (unsigned long long)gcr3_info->gcr3_tbl); - tmp = gcr3_info->glx; - target->data[0] |= (tmp & DTE_GLX_MASK) << DTE_GLX_SHIFT; - if (pdom_is_v2_pgtbl_mode(dev_data->domain)) - target->data[0] |= DTE_FLAG_GIOV; - target->data[0] |= DTE_FLAG_GV; - - gcr3 = iommu_virt_to_phys(gcr3_info->gcr3_tbl); - /* Encode GCR3 table into DTE */ - tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A; - target->data[0] |= tmp; - tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B; - tmp |= DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C; - target->data[1] |= tmp; + target->data[0] |= DTE_FLAG_GV | + FIELD_PREP(DTE_GLX, gcr3_info->glx) | + FIELD_PREP(DTE_GCR3_14_12, gcr3 >> 12); + if (pdom_is_v2_pgtbl_mode(dev_data->domain)) + target->data[0] |= DTE_FLAG_GIOV; + + target->data[1] |= FIELD_PREP(DTE_GCR3_30_15, gcr3 >> 15) | + FIELD_PREP(DTE_GCR3_51_31, gcr3 >> 31); /* Guest page table can only support 4 and 5 levels */ if (amd_iommu_gpt_level == PAGE_MODE_5_LEVEL) - target->data[2] |= ((u64)GUEST_PGTABLE_5_LEVEL << DTE_GPT_LEVEL_SHIFT); + target->data[2] |= + FIELD_PREP(DTE_GPT_LEVEL_MASK, GUEST_PGTABLE_5_LEVEL); + else + target->data[2] |= + FIELD_PREP(DTE_GPT_LEVEL_MASK, GUEST_PGTABLE_4_LEVEL); } static void set_dte_entry(struct amd_iommu *iommu,