From: Conor Dooley <conor@kernel.org>
To: linux-riscv@lists.infradead.org
Cc: conor@kernel.org, "Conor Dooley" <conor.dooley@microchip.com>,
xiao.w.wang@intel.com, "Andrew Jones" <ajones@ventanamicro.com>,
pulehui@huawei.com, "Charlie Jenkins" <charlie@rivosinc.com>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
linux-kernel@vger.kernel.org,
"Samuel Holland" <samuel.holland@sifive.com>,
"Pu Lehui" <pulehui@huaweicloud.com>,
"Björn Töpel" <bjorn@kernel.org>
Subject: [PATCH v4 0/2] RISC-V: clarify what some RISCV_ISA* config options do & redo Zbb toolchain dependency
Date: Thu, 24 Oct 2024 11:19:39 +0100 [thread overview]
Message-ID: <20241024-aspire-rectify-9982da6943e5@spud> (raw)
From: Conor Dooley <conor.dooley@microchip.com>
Since one depends on the other, albeit trivially, here's a v4 of the Zbb
toolchain dep removal alongside the rewording of Kconfig options I'd
sent out before the merge window. I think I like this implementation
better than v1, but I couldn't think of a good name for a "public"
version of __ALTERNATIVE(), so I used it here directly.
Unfortunately "ALTERNATIVE_2_CFG" already exists and I couldn't think of
a good way to name an alternative macro that allows for several config
options that didn't make the distinction sufficiently clear.. Yell
if you have better suggestions than I did.
I am a wee bit "worried" that this makes the Kconfig option confusing as
it isn't immediately obvious if someone is or is not going to get the
toolchain based optimisations.
Cheers,
Conor.
v4:
- rebase since it's been a few months
- change some wording Alex wasn't fond of in patch 1
- remove a left over CONFIG_RISCV_ISA_ZBB_ALT from the v1 implementation
in patch 2
CC: xiao.w.wang@intel.com
CC: Andrew Jones <ajones@ventanamicro.com>
CC: pulehui@huawei.com
CC: Charlie Jenkins <charlie@rivosinc.com>
CC: Paul Walmsley <paul.walmsley@sifive.com>
CC: Palmer Dabbelt <palmer@dabbelt.com>
CC: Conor Dooley <conor.dooley@microchip.com>
CC: linux-riscv@lists.infradead.org
CC: linux-kernel@vger.kernel.org
CC: Samuel Holland <samuel.holland@sifive.com>
CC: Pu Lehui <pulehui@huaweicloud.com>
CC: Björn Töpel <bjorn@kernel.org>
CC: Andrew Jones <ajones@ventanamicro.com>
CC: Paul Walmsley <paul.walmsley@sifive.com>
CC: Palmer Dabbelt <palmer@dabbelt.com>
CC: linux-riscv@lists.infradead.org
Conor Dooley (2):
RISC-V: clarify what some RISCV_ISA* config options do
RISC-V: separate Zbb optimisations requiring and not requiring
toolchain support
arch/riscv/Kconfig | 38 ++++++++++++++-------------
arch/riscv/include/asm/arch_hweight.h | 6 ++---
arch/riscv/include/asm/bitops.h | 4 +--
arch/riscv/include/asm/checksum.h | 3 +--
arch/riscv/lib/csum.c | 21 +++------------
arch/riscv/lib/strcmp.S | 5 ++--
arch/riscv/lib/strlen.S | 5 ++--
arch/riscv/lib/strncmp.S | 5 ++--
8 files changed, 38 insertions(+), 49 deletions(-)
--
2.45.2
next reply other threads:[~2024-10-24 10:19 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-24 10:19 Conor Dooley [this message]
2024-10-24 10:19 ` [PATCH v4 1/2] RISC-V: clarify what some RISCV_ISA* config options do Conor Dooley
2024-11-02 20:16 ` Samuel Holland
2025-01-03 0:31 ` Charlie Jenkins
2024-10-24 10:19 ` [PATCH v4 2/2] RISC-V: separate Zbb optimisations requiring and not requiring toolchain support Conor Dooley
2024-11-02 20:18 ` Samuel Holland
2025-01-03 0:32 ` Charlie Jenkins
2025-03-27 3:25 ` [PATCH v4 0/2] RISC-V: clarify what some RISCV_ISA* config options do & redo Zbb toolchain dependency patchwork-bot+linux-riscv
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