* drivers/clk/sophgo/clk-sg2042-pll.c:217:1-7: WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead.
@ 2024-10-24 14:49 kernel test robot
0 siblings, 0 replies; 2+ messages in thread
From: kernel test robot @ 2024-10-24 14:49 UTC (permalink / raw)
To: Chen Wang; +Cc: oe-kbuild-all, linux-kernel
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head: c2ee9f594da826bea183ed14f2cc029c719bf4da
commit: 48cf7e01386e7e35ea12255bc401bdd484c34e7d clk: sophgo: Add SG2042 clock driver
date: 4 months ago
config: loongarch-randconfig-r054-20241024 (https://download.01.org/0day-ci/archive/20241024/202410242248.o7XIZVqz-lkp@intel.com/config)
compiler: loongarch64-linux-gcc (GCC) 14.1.0
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202410242248.o7XIZVqz-lkp@intel.com/
cocci warnings: (new ones prefixed by >>)
>> drivers/clk/sophgo/clk-sg2042-pll.c:217:1-7: WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead.
>> drivers/clk/sophgo/clk-sg2042-pll.c:160:1-7: WARNING: do_div() does a 64-by-32 division, please consider using div64_u64 instead.
vim +217 drivers/clk/sophgo/clk-sg2042-pll.c
138
139 /**
140 * sg2042_pll_recalc_rate() - Calculate rate for plls
141 * @reg_value: current register value
142 * @parent_rate: parent frequency
143 *
144 * This function is used to calculate below "rate" in equation
145 * rate = (parent_rate/REFDIV) x FBDIV/POSTDIV1/POSTDIV2
146 * = (parent_rate x FBDIV) / (REFDIV x POSTDIV1 x POSTDIV2)
147 *
148 * Return: The rate calculated.
149 */
150 static unsigned long sg2042_pll_recalc_rate(unsigned int reg_value,
151 unsigned long parent_rate)
152 {
153 struct sg2042_pll_ctrl ctrl_table;
154 u64 numerator, denominator;
155
156 sg2042_pll_ctrl_decode(reg_value, &ctrl_table);
157
158 numerator = parent_rate * ctrl_table.fbdiv;
159 denominator = ctrl_table.refdiv * ctrl_table.postdiv1 * ctrl_table.postdiv2;
> 160 do_div(numerator, denominator);
161 return numerator;
162 }
163
164 /**
165 * sg2042_pll_get_postdiv_1_2() - Based on input rate/prate/fbdiv/refdiv,
166 * look up the postdiv1_2 table to get the closest postdiiv combination.
167 * @rate: FOUTPOSTDIV
168 * @prate: parent rate, i.e. FREF
169 * @fbdiv: FBDIV
170 * @refdiv: REFDIV
171 * @postdiv1: POSTDIV1, output
172 * @postdiv2: POSTDIV2, output
173 *
174 * postdiv1_2 contains all the possible combination lists of POSTDIV1 and POSTDIV2
175 * for example:
176 * postdiv1_2[0] = {2, 4, 8}, where div1 = 2, div2 = 4 , div1 * div2 = 8
177 *
178 * See TRM:
179 * FOUTPOSTDIV = FREF * FBDIV / REFDIV / (POSTDIV1 * POSTDIV2)
180 * So we get following formula to get POSTDIV1 and POSTDIV2:
181 * POSTDIV = (prate/REFDIV) x FBDIV/rate
182 * above POSTDIV = POSTDIV1*POSTDIV2
183 *
184 * Return:
185 * %0 - OK
186 * %-EINVAL - invalid argument, which means Failed to get the postdivs.
187 */
188 static int sg2042_pll_get_postdiv_1_2(unsigned long rate,
189 unsigned long prate,
190 unsigned int fbdiv,
191 unsigned int refdiv,
192 unsigned int *postdiv1,
193 unsigned int *postdiv2)
194 {
195 int index;
196 u64 tmp0;
197
198 /* POSTDIV_RESULT_INDEX point to 3rd element in the array postdiv1_2 */
199 #define POSTDIV_RESULT_INDEX 2
200
201 static const int postdiv1_2[][3] = {
202 {2, 4, 8}, {3, 3, 9}, {2, 5, 10}, {2, 6, 12},
203 {2, 7, 14}, {3, 5, 15}, {4, 4, 16}, {3, 6, 18},
204 {4, 5, 20}, {3, 7, 21}, {4, 6, 24}, {5, 5, 25},
205 {4, 7, 28}, {5, 6, 30}, {5, 7, 35}, {6, 6, 36},
206 {6, 7, 42}, {7, 7, 49}
207 };
208
209 /* prate/REFDIV and result save to tmp0 */
210 tmp0 = prate;
211 do_div(tmp0, refdiv);
212
213 /* ((prate/REFDIV) x FBDIV) and result save to tmp0 */
214 tmp0 *= fbdiv;
215
216 /* ((prate/REFDIV) x FBDIV)/rate and result save to tmp0 */
> 217 do_div(tmp0, rate);
218
219 /* tmp0 is POSTDIV1*POSTDIV2, now we calculate div1 and div2 value */
220 if (tmp0 <= 7) {
221 /* (div1 * div2) <= 7, no need to use array search */
222 *postdiv1 = tmp0;
223 *postdiv2 = 1;
224 return 0;
225 }
226
227 /* (div1 * div2) > 7, use array search */
228 for (index = 0; index < ARRAY_SIZE(postdiv1_2); index++) {
229 if (tmp0 > postdiv1_2[index][POSTDIV_RESULT_INDEX]) {
230 continue;
231 } else {
232 /* found it */
233 *postdiv1 = postdiv1_2[index][1];
234 *postdiv2 = postdiv1_2[index][0];
235 return 0;
236 }
237 }
238 pr_warn("%s can not find in postdiv array!\n", __func__);
239 return -EINVAL;
240 }
241
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 2+ messages in thread
* drivers/clk/sophgo/clk-sg2042-pll.c:217:1-7: WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead.
@ 2025-04-05 7:04 kernel test robot
0 siblings, 0 replies; 2+ messages in thread
From: kernel test robot @ 2025-04-05 7:04 UTC (permalink / raw)
To: Chen Wang; +Cc: oe-kbuild-all, linux-kernel
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head: a8662bcd2ff152bfbc751cab20f33053d74d0963
commit: 48cf7e01386e7e35ea12255bc401bdd484c34e7d clk: sophgo: Add SG2042 clock driver
date: 10 months ago
config: arm-randconfig-r053-20250404 (https://download.01.org/0day-ci/archive/20250405/202504051456.niworhgJ-lkp@intel.com/config)
compiler: clang version 21.0.0git (https://github.com/llvm/llvm-project 7eccafc3c84606587a175c0a8c1ebea6e4fb21cd)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202504051456.niworhgJ-lkp@intel.com/
cocci warnings: (new ones prefixed by >>)
>> drivers/clk/sophgo/clk-sg2042-pll.c:217:1-7: WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead.
>> drivers/clk/sophgo/clk-sg2042-pll.c:160:1-7: WARNING: do_div() does a 64-by-32 division, please consider using div64_u64 instead.
vim +217 drivers/clk/sophgo/clk-sg2042-pll.c
138
139 /**
140 * sg2042_pll_recalc_rate() - Calculate rate for plls
141 * @reg_value: current register value
142 * @parent_rate: parent frequency
143 *
144 * This function is used to calculate below "rate" in equation
145 * rate = (parent_rate/REFDIV) x FBDIV/POSTDIV1/POSTDIV2
146 * = (parent_rate x FBDIV) / (REFDIV x POSTDIV1 x POSTDIV2)
147 *
148 * Return: The rate calculated.
149 */
150 static unsigned long sg2042_pll_recalc_rate(unsigned int reg_value,
151 unsigned long parent_rate)
152 {
153 struct sg2042_pll_ctrl ctrl_table;
154 u64 numerator, denominator;
155
156 sg2042_pll_ctrl_decode(reg_value, &ctrl_table);
157
158 numerator = parent_rate * ctrl_table.fbdiv;
159 denominator = ctrl_table.refdiv * ctrl_table.postdiv1 * ctrl_table.postdiv2;
> 160 do_div(numerator, denominator);
161 return numerator;
162 }
163
164 /**
165 * sg2042_pll_get_postdiv_1_2() - Based on input rate/prate/fbdiv/refdiv,
166 * look up the postdiv1_2 table to get the closest postdiiv combination.
167 * @rate: FOUTPOSTDIV
168 * @prate: parent rate, i.e. FREF
169 * @fbdiv: FBDIV
170 * @refdiv: REFDIV
171 * @postdiv1: POSTDIV1, output
172 * @postdiv2: POSTDIV2, output
173 *
174 * postdiv1_2 contains all the possible combination lists of POSTDIV1 and POSTDIV2
175 * for example:
176 * postdiv1_2[0] = {2, 4, 8}, where div1 = 2, div2 = 4 , div1 * div2 = 8
177 *
178 * See TRM:
179 * FOUTPOSTDIV = FREF * FBDIV / REFDIV / (POSTDIV1 * POSTDIV2)
180 * So we get following formula to get POSTDIV1 and POSTDIV2:
181 * POSTDIV = (prate/REFDIV) x FBDIV/rate
182 * above POSTDIV = POSTDIV1*POSTDIV2
183 *
184 * Return:
185 * %0 - OK
186 * %-EINVAL - invalid argument, which means Failed to get the postdivs.
187 */
188 static int sg2042_pll_get_postdiv_1_2(unsigned long rate,
189 unsigned long prate,
190 unsigned int fbdiv,
191 unsigned int refdiv,
192 unsigned int *postdiv1,
193 unsigned int *postdiv2)
194 {
195 int index;
196 u64 tmp0;
197
198 /* POSTDIV_RESULT_INDEX point to 3rd element in the array postdiv1_2 */
199 #define POSTDIV_RESULT_INDEX 2
200
201 static const int postdiv1_2[][3] = {
202 {2, 4, 8}, {3, 3, 9}, {2, 5, 10}, {2, 6, 12},
203 {2, 7, 14}, {3, 5, 15}, {4, 4, 16}, {3, 6, 18},
204 {4, 5, 20}, {3, 7, 21}, {4, 6, 24}, {5, 5, 25},
205 {4, 7, 28}, {5, 6, 30}, {5, 7, 35}, {6, 6, 36},
206 {6, 7, 42}, {7, 7, 49}
207 };
208
209 /* prate/REFDIV and result save to tmp0 */
210 tmp0 = prate;
211 do_div(tmp0, refdiv);
212
213 /* ((prate/REFDIV) x FBDIV) and result save to tmp0 */
214 tmp0 *= fbdiv;
215
216 /* ((prate/REFDIV) x FBDIV)/rate and result save to tmp0 */
> 217 do_div(tmp0, rate);
218
219 /* tmp0 is POSTDIV1*POSTDIV2, now we calculate div1 and div2 value */
220 if (tmp0 <= 7) {
221 /* (div1 * div2) <= 7, no need to use array search */
222 *postdiv1 = tmp0;
223 *postdiv2 = 1;
224 return 0;
225 }
226
227 /* (div1 * div2) > 7, use array search */
228 for (index = 0; index < ARRAY_SIZE(postdiv1_2); index++) {
229 if (tmp0 > postdiv1_2[index][POSTDIV_RESULT_INDEX]) {
230 continue;
231 } else {
232 /* found it */
233 *postdiv1 = postdiv1_2[index][1];
234 *postdiv2 = postdiv1_2[index][0];
235 return 0;
236 }
237 }
238 pr_warn("%s can not find in postdiv array!\n", __func__);
239 return -EINVAL;
240 }
241
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 2+ messages in thread
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