[RFC PATCH 2/2] dt-bindings: spi: Update stacked and parallel bindings

[Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>]

For implementing the proposed solution the current 'stacked-memories' &
'parallel-memories' bindings need to be updated as follow.

stacked-memories binding changes:
- Each flash will have its own flash node. This approach allows flashes of
  different makes and sizes to be stacked together, as each flash will be
  probed individually.
- Each of the flash node will have its own “reg” property that will contain
  its physical CS.
- Remove the size information from the bindings as it can be retrived
  drirectly from the flash.
- The stacked-memories DT bindings will contain the phandles of the flash
  nodes connected in stacked mode.

The new layer will update the mtd->size and other mtd_info parameters after
both the flashes are probed and will call mtd_device_register with the
combined information.

spi@0 {
        ...
        flash@0 {
                compatible = "jedec,spi-nor"
                reg = <0x00>;
                stacked-memories = <&flash@0 &flash@1>;
                spi-max-frequency = <50000000>;
                ...
                        partitions {
                        compatible = "fixed-partitions";
                                concat-partition = <&flash0_partition &flash1_partition>;
                                flash0_partition: partition@0 {
                                        label = "part0_0";
                                        reg = <0x0 0x800000>;
                                }
                        }
        }
        flash@1 {
                compatible = "jedec,spi-nor"
                reg = <0x01>;
                stacked-memories = <&flash@0 &flash@1>;
                spi-max-frequency = <50000000>;
                ...
                        partitions {
                        compatible = "fixed-partitions";
                                concat-partition = <&flash0_partition &flash1_partition>;
                                flash1_partition: partition@0 {
                                        label = "part0_1";
                                        reg = <0x0 0x800000>;
                                }
                        }
        }

}

parallel-memories binding changes:
- Remove the size information from the bindings and change the type to
  boolen.
- Each flash connected in parallel mode should be identical and will have
  one flash node for both the flash devices.
- The “reg” prop will contain the physical CS number for both the connected
  flashes.

The new layer will double the mtd-> size and register it with the mtd layer.

spi@1 {
        ...
        flash@3 {
                compatible = "jedec,spi-nor"
                reg = <0x00 0x01>;
                paralle-memories ;
                spi-max-frequency = <50000000>;
                ...
                        partitions {
                        compatible = "fixed-partitions";
                                flash0_partition: partition@0 {
                                        label = "part0_0";
                                        reg = <0x0 0x800000>;
                                }
                        }
        }
}

Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>
---
 .../bindings/spi/spi-controller.yaml          | 23 +++++++++++++++++--
 .../bindings/spi/spi-peripheral-props.yaml    |  9 +++-----
 2 files changed, 24 insertions(+), 8 deletions(-)

diff --git a/Documentation/devicetree/bindings/spi/spi-controller.yaml b/Documentation/devicetree/bindings/spi/spi-controller.yaml
index 093150c0cb87..2d300f98dd72 100644
--- a/Documentation/devicetree/bindings/spi/spi-controller.yaml
+++ b/Documentation/devicetree/bindings/spi/spi-controller.yaml
@@ -185,7 +185,26 @@ examples:
         flash@2 {
             compatible = "jedec,spi-nor";
             spi-max-frequency = <50000000>;
-            reg = <2>, <3>;
-            stacked-memories = /bits/ 64 <0x10000000 0x10000000>;
+            reg = <2>;
+            stacked-memories = <&flash0 &flash1>;
         };
+
     };
+
+  - |
+    spi@90010000 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        compatible = "fsl,imx28-spi";
+        reg = <0x90010000 0x2000>;
+        interrupts = <96>;
+        dmas = <&dma_apbh 0>;
+        dma-names = "rx-tx";
+
+        flash@0 {
+            compatible = "jedec,spi-nor";
+            spi-max-frequency = <50000000>;
+            reg = <0>, <1>;
+            parallel-memories;
+        };
+      };
diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
index 15938f81fdce..2a014160d701 100644
--- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
+++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
@@ -96,7 +96,7 @@ properties:
       space with only a single additional wire, while still needing
       to repeat the commands when crossing a chip boundary. The size of
       each chip should be provided as members of the array.
-    $ref: /schemas/types.yaml#/definitions/uint64-array
+    $ref: /schemas/types.yaml#/definitions/phandle-array
     minItems: 2
     maxItems: 4
 
@@ -107,11 +107,8 @@ properties:
       different memories (eg. even bits are stored in one memory, odd
       bits in the other). This basically doubles the address space and
       the throughput while greatly complexifying the wiring because as
-      many busses as devices must be wired. The size of each chip should
-      be provided as members of the array.
-    $ref: /schemas/types.yaml#/definitions/uint64-array
-    minItems: 2
-    maxItems: 4
+      many busses as devices must be wired.
+    $ref: /schemas/types.yaml#/definitions/flag
 
   st,spi-midi-ns:
     description: |
-- 
2.34.1