[PATCHv3 16/22] ARM: dts: socfpga: add Enclustra Mercury+ SA2

Lothar Rubusch
2024-10-27T14:37:19Z

Introduce Enclustra's Mercury+ SA2 SoM based on Intel Cyclone5
technology as a .dtsi file.

Signed-off-by: Andreas Buerkler <andreas.buerkler@enclustra.com>
Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
---
.../socfpga/socfpga_cyclone5_mercury_sa2.dtsi | 146 ++++++++++++++++++
1 file changed, 146 insertions(+)
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2.dtsi

diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2.dtsi
new file mode 100644
index 000000000..0425520e9
--- /dev/null
+++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2.dtsi
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
+ */
+
+#include "socfpga_cyclone5.dtsi"
+
+/ {
+ model = "Enclustra Mercury+ SA2";
+ compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ ethernet0 = &gmac1;
+ };
+
+ /* Adjusted the i2c labels to use generic base-board dtsi files for
+ * Enclustra Arria10 and Cyclone5 SoMs.
+ *
+ * The set of i2c0 and i2c1 labels defined in socfpga_cyclone5.dtsi and in
+ * socfpga_arria10.dtsi do not allow for using the same base-board .dtsi
+ * fragments. Thus define generic labels here to match the correct i2c
+ * bus in a generic base-board .dtsi file.
+ */
+ soc {
+ i2c_encl: i2c@ffc04000 {
+ };
+ i2c_encl_fpga: i2c@ffc05000 {
+ };
+ };
+
+ memory {
+ name = "memory";
+ device_type = "memory";
+ reg = <0x0 0x80000000>; /* 2GB */
+ };
+};
+
+&osc1 {
+ clock-frequency = <50000000>;
+};
+
+&i2c_encl {
+ i2c-sda-hold-time-ns = <300>;
+ clock-frequency = <100000>;
+ status = "okay";
+
+ isl12020: isl12020@6f {
+ compatible = "isil,isl12022";
+ reg = <0x6f>;
+ };
+
+ atsha204a: atsha204a@64 {
+ compatible = "atmel,atsha204a";
+ reg = <0x64>;
+ };
+};
+
+&i2c_encl_fpga {
+ i2c-sda-hold-time-ns = <300>;
+ status = "disabled";
+};
+
+&uart0 {
+ clock-frequency = <100000000>;
+};
+
+&mmc0 {
+ status = "okay";
+};
+
+&qspi {
+ status = "okay";
+
+ flash0: s25fl512s@0 {
+ u-boot,dm-pre-reloc;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spansion,s25fl512s", "jedec,spi-nor";
+ reg = <0>;
+
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ spi-max-frequency = <10000000>;
+
+ cdns,read-delay = <4>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
+
+ partition@raw {
+ label = "Flash Raw";
+ reg = <0x0 0x4000000>;
+ };
+ };
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gmac1 {
+ status = "okay";
+ /delete-property/ mac-address;
+ phy-mode = "rgmii";
+ phy-handle = <&phy3>;
+
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ phy3: ethernet-phy@3 {
+ reg = <3>;
+
+ /* Add 2ns RX clock delay (1.2ns + 0.78ns)*/
+ rxc-skew-ps = <1680>;
+ rxd0-skew-ps = <420>;
+ rxd1-skew-ps = <420>;
+ rxd2-skew-ps = <420>;
+ rxd3-skew-ps = <420>;
+ rxdv-skew-ps = <420>;
+
+ /* Add 1.38ns TX clock delay (0.96ns + 0.42ns)*/
+ txc-skew-ps = <1860>;
+ txd0-skew-ps = <0>;
+ txd1-skew-ps = <0>;
+ txd2-skew-ps = <0>;
+ txd3-skew-ps = <0>;
+ txen-skew-ps = <0>;
+ };
+ };
+};
+
+&usb1 {
+ status = "okay";
+ dr_mode = "host";
+};
--
2.25.1