From: Christoph Hellwig <hch@lst.de>
To: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Cc: Christoph Hellwig <hch@lst.de>,
Konrad Dybcio <konradybcio@kernel.org>,
Keith Busch <kbusch@kernel.org>, Jens Axboe <axboe@kernel.dk>,
Sagi Grimberg <sagi@grimberg.me>,
Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>,
Marijn Suijten <marijn.suijten@somainline.org>,
linux-nvme@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] nvme-pci: Force NVME_QUIRK_SIMPLE_SUSPEND on Qualcomm hosts
Date: Mon, 28 Oct 2024 10:19:41 +0100 [thread overview]
Message-ID: <20241028091941.GA29461@lst.de> (raw)
In-Reply-To: <0fac5de3-3f35-4fc2-bbdc-411dc1018a85@oss.qualcomm.com>
On Fri, Oct 25, 2024 at 05:30:05PM +0200, Konrad Dybcio wrote:
> (Un?)fortunately, said platforms use FDT, so we can't fix that in ACPI.
Then generalize the acpi helper to a generic one checking ACPI and
DT and specify a proper DT binding.
If th requirement to put all devices into D3 is a plaform propery
a specific driver is always the wrong place for it.
> b) Adding such a property to the PCIe host node sounds a bit
> saner, but the NVMe code isn't aware of the RC. We could add
> something like:
Again, this all belongs into core code. The nvme driver is just
a consumer of this information, just like for example the AHCI
driver.
next prev parent reply other threads:[~2024-10-28 9:19 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-24 17:33 [PATCH] nvme-pci: Force NVME_QUIRK_SIMPLE_SUSPEND on Qualcomm hosts Konrad Dybcio
2024-10-25 11:35 ` Christoph Hellwig
2024-10-25 15:30 ` Konrad Dybcio
2024-10-28 9:19 ` Christoph Hellwig [this message]
2024-10-28 13:15 ` Konrad Dybcio
2024-10-25 16:12 ` Keith Busch
2024-10-25 16:40 ` Konrad Dybcio
2024-10-25 16:57 ` Keith Busch
2024-10-25 17:20 ` Konrad Dybcio
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