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[209.17.68.221]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-211056eda38sm49800595ad.48.2024.11.03.12.47.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 12:47:18 -0800 (PST) Date: Mon, 4 Nov 2024 05:47:16 +0900 From: Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= To: Jian-Hong Pan Cc: Bjorn Helgaas , Johan Hovold , David Box , Ilpo =?utf-8?B?SsOkcnZpbmVu?= , Kuppuswamy Sathyanarayanan , Nirmal Patel , Jonathan Derrick , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux@endlessos.org Subject: Re: [PATCH v12 3/3] PCI/ASPM: Make pci_save_aspm_l1ss_state save both child and parent's L1SS configuration Message-ID: <20241103204716.GE237624@rocinante> References: <20241001083438.10070-2-jhp@endlessos.org> <20241001083438.10070-8-jhp@endlessos.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20241001083438.10070-8-jhp@endlessos.org> Hello, > PCI devices' parameters on the VMD bus have been programmed properly > originally. But, cleared after pci_reset_bus() and have not been restored > correctly. This leads the link's L1.2 between PCIe Root Port and child > device gets wrong configs. > > Here is a failed example on ASUS B1400CEAE with enabled VMD. Both PCIe > bridge and NVMe device should have the same LTR1.2_Threshold value. > However, they are configured as different values in this case: > > 10000:e0:06.0 PCI bridge [0604]: Intel Corporation 11th Gen Core Processor PCIe Controller [8086:9a09] (rev 01) (prog-if 00 [Normal decode]) > ... > Capabilities: [200 v1] L1 PM Substates > L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+ > PortCommonModeRestoreTime=45us PortTPowerOnTime=50us > L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2+ ASPM_L1.1- > T_CommonMode=0us LTR1.2_Threshold=0ns > L1SubCtl2: T_PwrOn=0us > > 10000:e1:00.0 Non-Volatile memory controller [0108]: Sandisk Corp WD Blue SN550 NVMe SSD [15b7:5009] (rev 01) (prog-if 02 [NVM Express]) > ... > Capabilities: [900 v1] L1 PM Substates > L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1- ASPM_L1.2+ ASPM_L1.1- L1_PM_Substates+ > PortCommonModeRestoreTime=32us PortTPowerOnTime=10us > L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2+ ASPM_L1.1- > T_CommonMode=0us LTR1.2_Threshold=101376ns > L1SubCtl2: T_PwrOn=50us > > Here is VMD mapped PCI device tree: > > -+-[0000:00]-+-00.0 Intel Corporation Device 9a04 > | ... > \-[10000:e0]-+-06.0-[e1]----00.0 Sandisk Corp WD Blue SN550 NVMe SSD > \-17.0 Intel Corporation Tiger Lake-LP SATA Controller > > When pci_reset_bus() resets the bus [e1] of the NVMe, it only saves and > restores NVMe's state before and after reset. Then, when it restores the > NVMe's state, ASPM code restores L1SS for both the parent bridge and the > NVMe in pci_restore_aspm_l1ss_state(). The NVMe's L1SS is restored > correctly. But, the parent bridge's L1SS is restored with a wrong value 0x0 > because the parent bridge's L1SS wasn't saved by pci_save_aspm_l1ss_state() > before reset. > > So, if the PCI device has a parent, make pci_save_aspm_l1ss_state() save > the parent's L1SS configuration, too. This is symmetric on > pci_restore_aspm_l1ss_state(). Applied to aspm, thank you! [01/02] PCI/ASPM: Add notes about enabling PCI-PM L1SS to pci_enable_link_state(_locked) https://git.kernel.org/pci/pci/c/4681da23786a [02/02] PCI/ASPM: Make pci_save_aspm_l1ss_state save both child and parent's L1SS configuration https://git.kernel.org/pci/pci/c/1f37e72d586f Krzysztof