Re: [PATCH v9 03/10] asm/rwonce: Introduce [READ|WRITE]_ONCE() support for __int128

[Jason Gunthorpe <jgg@nvidia.com>]

On Thu, Nov 07, 2024 at 11:01:58AM +0100, Arnd Bergmann wrote:

> >> and later:
> >> 
> >>  * Yes, this permits 64-bit accesses on 32-bit architectures. These will
> >>  * actually be atomic in some cases (namely Armv7 + LPAE), but for others we
> >>  * rely on the access being split into 2x32-bit accesses for a 32-bit quantity
> >>  * (e.g. a virtual address) and a strong prevailing wind.
> >> 
> >> This is the "strong prevailing wind", mentioned in the patch review at [1].
> >> 
> >> [1] https://lore.kernel.org/lkml/20241016130819.GJ3559746@nvidia.com/
> 
> I understand the special case for ARMv7VE. I think the more important
> comment in that file is
> 
>   * Use __READ_ONCE() instead of READ_ONCE() if you do not require any
>   * atomicity. Note that this may result in tears!

That makes sense, let's just use that and there is no need to change
anything here?

Uros?

> >> FYI, Processors with AVX guarantee 128bit atomic access with SSE
> >> 128bit move instructions, see e.g. [2].
> >> 
> >> [2] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104688
> 
> AVX instructions are not used in the kernel. If you want atomic
> loads, that has to rely on architecture specific instructions
> like cmpxchg16b on x86-64 or ldp on arm64. Actually using these
> requires checking the system_has_cmpxchg128() macro.

Yeah, that is what this series is doing..

Jason