From: Krishna chaitanya chundru <quic_krichai@quicinc.com>
To: andersson@kernel.org, "Bjorn Helgaas" <bhelgaas@google.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Konrad Dybcio" <konradybcio@kernel.org>,
cros-qcom-dts-watchers@chromium.org,
"Jingoo Han" <jingoohan1@gmail.com>,
"Bartosz Golaszewski" <brgl@bgdev.pl>
Cc: <quic_vbadigan@quicinc.com>, <linux-arm-msm@vger.kernel.org>,
<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
Krishna chaitanya chundru <quic_krichai@quicinc.com>
Subject: [PATCH v3 2/6] arm64: dts: qcom: qcs6490-rb3gen2: Add node for qps615
Date: Tue, 12 Nov 2024 20:31:34 +0530 [thread overview]
Message-ID: <20241112-qps615_pwr-v3-2-29a1e98aa2b0@quicinc.com> (raw)
In-Reply-To: <20241112-qps615_pwr-v3-0-29a1e98aa2b0@quicinc.com>
Add QPS615 PCIe switch node which has 3 downstream ports and in one
downstream port two embedded ethernet devices are present.
Power to the QPS615 is supplied through two LDO regulators, controlled
by two GPIOs, these are added as fixed regulators. And the QPS615 is
configured through i2c.
Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
---
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 115 +++++++++++++++++++++++++++
arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +-
2 files changed, 116 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
index 0d45662b8028..0e890841b600 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
@@ -202,6 +202,30 @@ vph_pwr: vph-pwr-regulator {
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
};
+
+ vdd_ntn_0p9: regulator-vdd-ntn-0p9 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_NTN_0P9";
+ gpio = <&pm8350c_gpios 2 GPIO_ACTIVE_HIGH>;
+ regulator-min-microvolt = <899400>;
+ regulator-max-microvolt = <899400>;
+ enable-active-high;
+ pinctrl-0 = <&ntn_0p9_en>;
+ pinctrl-names = "default";
+ regulator-enable-ramp-delay = <4300>;
+ };
+
+ vdd_ntn_1p8: regulator-vdd-ntn-1p8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_NTN_1P8";
+ gpio = <&pm8350c_gpios 3 GPIO_ACTIVE_HIGH>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ enable-active-high;
+ pinctrl-0 = <&ntn_1p8_en>;
+ pinctrl-names = "default";
+ regulator-enable-ramp-delay = <10000>;
+ };
};
&apps_rsc {
@@ -684,6 +708,75 @@ &mdss_edp_phy {
status = "okay";
};
+&pcie1_port {
+ pcie@0,0 {
+ compatible = "pci1179,0623";
+ reg = <0x10000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ ranges;
+ bus-range = <0x2 0xff>;
+
+ vddc-supply = <&vdd_ntn_0p9>;
+ vdd18-supply = <&vdd_ntn_1p8>;
+ vdd09-supply = <&vdd_ntn_0p9>;
+ vddio1-supply = <&vdd_ntn_1p8>;
+ vddio2-supply = <&vdd_ntn_1p8>;
+ vddio18-supply = <&vdd_ntn_1p8>;
+
+ i2c-parent = <&i2c0 0x77>;
+
+ reset-gpios = <&pm8350c_gpios 1 GPIO_ACTIVE_LOW>;
+
+ pcie@1,0 {
+ reg = <0x20800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ ranges;
+ bus-range = <0x3 0xff>;
+ };
+
+ pcie@2,0 {
+ reg = <0x21000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ ranges;
+ bus-range = <0x4 0xff>;
+ };
+
+ pcie@3,0 {
+ reg = <0x21800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges;
+ bus-range = <0x5 0xff>;
+
+ pcie@0,0 {
+ reg = <0x50000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges;
+ };
+
+ pcie@0,1 {
+ reg = <0x50100 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges;
+ };
+ };
+ };
+};
+
&pmk8350_rtc {
status = "okay";
};
@@ -812,6 +905,28 @@ lt9611_rst_pin: lt9611-rst-state {
};
};
+&pm8350c_gpios {
+ ntn_0p9_en: ntn-0p9-en-state {
+ pins = "gpio2";
+ function = "normal";
+
+ bias-disable;
+ input-disable;
+ output-enable;
+ power-source = <0>;
+ };
+
+ ntn_1p8_en: ntn-1p8-en-state {
+ pins = "gpio3";
+ function = "normal";
+
+ bias-disable;
+ input-disable;
+ output-enable;
+ power-source = <0>;
+ };
+};
+
&tlmm {
lt9611_irq_pin: lt9611-irq-state {
pins = "gpio24";
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 3d8410683402..82434f085ff0 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -2279,7 +2279,7 @@ pcie1: pcie@1c08000 {
status = "disabled";
- pcie@0 {
+ pcie1_port: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
--
2.34.1
next prev parent reply other threads:[~2024-11-12 15:02 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-12 15:01 [PATCH v3 0/6] PCI: Enable Power and configure the QPS615 PCIe switch Krishna chaitanya chundru
2024-11-12 15:01 ` [PATCH v3 1/6] dt-bindings: PCI: Add binding for qps615 Krishna chaitanya chundru
2024-11-12 15:49 ` Bjorn Andersson
2024-11-15 16:18 ` Rob Herring
2024-11-20 8:04 ` Krzysztof Kozlowski
2024-11-12 15:01 ` Krishna chaitanya chundru [this message]
2024-11-12 15:49 ` [PATCH v3 2/6] arm64: dts: qcom: qcs6490-rb3gen2: Add node " Bjorn Andersson
2024-11-15 11:45 ` Manivannan Sadhasivam
2024-11-20 8:06 ` Krzysztof Kozlowski
2024-11-20 11:03 ` Dmitry Baryshkov
2024-11-12 15:01 ` [PATCH v3 3/6] PCI: Add new start_link() & stop_link function ops Krishna chaitanya chundru
2024-11-12 23:41 ` Bjorn Helgaas
2024-11-13 8:41 ` Krishna Chaitanya Chundru
2024-11-15 11:51 ` Manivannan Sadhasivam
2024-11-12 15:01 ` [PATCH v3 4/6] PCI: dwc: Add support for new pci function op Krishna chaitanya chundru
2024-11-12 23:32 ` Bjorn Helgaas
2024-11-12 15:01 ` [PATCH v3 5/6] PCI: qcom: Add support for host_stop_link() & host_start_link() Krishna chaitanya chundru
2024-11-12 23:36 ` Bjorn Helgaas
2024-11-15 11:57 ` Manivannan Sadhasivam
2024-11-12 15:01 ` [PATCH v3 6/6] PCI: pwrctl: Add power control driver for qps615 Krishna chaitanya chundru
2024-11-12 15:51 ` Bjorn Andersson
2024-11-12 23:21 ` Bjorn Andersson
2024-11-13 13:38 ` Bartosz Golaszewski
2024-11-15 12:25 ` Manivannan Sadhasivam
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