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charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20241112-qps615_pwr-v3-2-29a1e98aa2b0@quicinc.com> On Tue, Nov 12, 2024 at 08:31:34PM +0530, Krishna chaitanya chundru wrote: > Add QPS615 PCIe switch node which has 3 downstream ports and in one > downstream port two embedded ethernet devices are present. > > Power to the QPS615 is supplied through two LDO regulators, controlled > by two GPIOs, these are added as fixed regulators. And the QPS615 is > configured through i2c. > > Signed-off-by: Krishna chaitanya chundru Acked-by: Manivannan Sadhasivam One comment below. > --- > arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 115 +++++++++++++++++++++++++++ > arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- > 2 files changed, 116 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts > index 0d45662b8028..0e890841b600 100644 > --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts > +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts > @@ -202,6 +202,30 @@ vph_pwr: vph-pwr-regulator { > regulator-min-microvolt = <3700000>; > regulator-max-microvolt = <3700000>; > }; > + > + vdd_ntn_0p9: regulator-vdd-ntn-0p9 { > + compatible = "regulator-fixed"; > + regulator-name = "VDD_NTN_0P9"; > + gpio = <&pm8350c_gpios 2 GPIO_ACTIVE_HIGH>; > + regulator-min-microvolt = <899400>; > + regulator-max-microvolt = <899400>; > + enable-active-high; > + pinctrl-0 = <&ntn_0p9_en>; > + pinctrl-names = "default"; > + regulator-enable-ramp-delay = <4300>; > + }; > + > + vdd_ntn_1p8: regulator-vdd-ntn-1p8 { > + compatible = "regulator-fixed"; > + regulator-name = "VDD_NTN_1P8"; > + gpio = <&pm8350c_gpios 3 GPIO_ACTIVE_HIGH>; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + enable-active-high; > + pinctrl-0 = <&ntn_1p8_en>; > + pinctrl-names = "default"; > + regulator-enable-ramp-delay = <10000>; > + }; > }; > > &apps_rsc { > @@ -684,6 +708,75 @@ &mdss_edp_phy { > status = "okay"; > }; > > +&pcie1_port { > + pcie@0,0 { > + compatible = "pci1179,0623"; > + reg = <0x10000 0x0 0x0 0x0 0x0>; > + #address-cells = <3>; > + #size-cells = <2>; > + > + device_type = "pci"; > + ranges; > + bus-range = <0x2 0xff>; > + > + vddc-supply = <&vdd_ntn_0p9>; > + vdd18-supply = <&vdd_ntn_1p8>; > + vdd09-supply = <&vdd_ntn_0p9>; > + vddio1-supply = <&vdd_ntn_1p8>; > + vddio2-supply = <&vdd_ntn_1p8>; > + vddio18-supply = <&vdd_ntn_1p8>; > + > + i2c-parent = <&i2c0 0x77>; > + > + reset-gpios = <&pm8350c_gpios 1 GPIO_ACTIVE_LOW>; > + > + pcie@1,0 { > + reg = <0x20800 0x0 0x0 0x0 0x0>; > + #address-cells = <3>; > + #size-cells = <2>; > + > + device_type = "pci"; > + ranges; > + bus-range = <0x3 0xff>; > + }; > + > + pcie@2,0 { > + reg = <0x21000 0x0 0x0 0x0 0x0>; > + #address-cells = <3>; > + #size-cells = <2>; > + > + device_type = "pci"; > + ranges; > + bus-range = <0x4 0xff>; > + }; > + > + pcie@3,0 { > + reg = <0x21800 0x0 0x0 0x0 0x0>; > + #address-cells = <3>; > + #size-cells = <2>; > + device_type = "pci"; > + ranges; > + bus-range = <0x5 0xff>; > + You haven't added any additional properties (dfe etc...) to any of the downstream port nodes. Does this mean that this board doesn't need any of them? - Mani -- மணிவண்ணன் சதாசிவம்