From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C46A918E047; Fri, 15 Nov 2024 16:39:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731688783; cv=none; b=WTvXDjC+495dDDD9QISkBk7UOpRseNRnA2o+hG3lD/3COP0V+IPFGAXRjiMQ8vaStJvITgLD363/Vh0DRRkk2WoeyOyAEHEetwZA/b2gM0GePxIvxOpiXYNZ2bGghqgCrmH2tSkeYIPB/u5vbbBqqpWwrJs1I6o6c4Wlpc84Ohg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731688783; c=relaxed/simple; bh=iRr3qC8xf3SocAeyPSOv4BEKnzUJ3YHOuClfGqNnj3o=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=WVjbW8zTM32g1Oy4tzz+m3iHctRiZT1jmphbHuBEomCeR/cuR0BK93IgoGxs9sajontM4keF/KHLL4bk6u/2R42sOHBB43r/UxoiSaeMxksyfmWjEmkhh9Vmvm1mND9bXZ3EeCATQapvBchrR6nak5Z04oMGIo3Ps15gbY28FrA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=AP/GnWwj; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="AP/GnWwj" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2EC12C4CECF; Fri, 15 Nov 2024 16:39:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1731688783; bh=iRr3qC8xf3SocAeyPSOv4BEKnzUJ3YHOuClfGqNnj3o=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=AP/GnWwjAUJLjLFoxgVufPIRcVQsuuCixNyxHBMNXq00d0lDhi+r0CB0ZJyC99XZi sglwDivb/koS7axFD0SOzdC8byWidw6FjVRON36PCqYXjefKXEypjAo1Ut5Tw3b3t1 21q5Vn5Rb9IiF+fSp1XkK4qrm1FqkLpuidYcI+JgbOwnIrm9OxK7PxNJCVNfp07vdN 0+g/2/cgwY+a8Dck3dFLWhcc4o3yUAGyz9kkLlXx1e/UELEajk5UaqMar2+KG8ZSUy eSKBCwOH2KxJ5A9fhdO0qtf9YW0ajNRR2cBP/vRBSJJyeZwvEaU8jtIcQQz8vSIV6o 48KUb5iGtj3gg== Date: Fri, 15 Nov 2024 10:39:41 -0600 From: Rob Herring To: Christian Bruel Cc: lpieralisi@kernel.org, kw@linux.com, manivannan.sadhasivam@linaro.org, bhelgaas@google.com, krzk+dt@kernel.org, conor+dt@kernel.org, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, p.zabel@pengutronix.de, cassel@kernel.org, quic_schintav@quicinc.com, fabrice.gasnier@foss.st.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 3/5] dt-bindings: PCI: Add STM32MP25 PCIe endpoint bindings Message-ID: <20241115163941.GA3324312-robh@kernel.org> References: <20241112161925.999196-1-christian.bruel@foss.st.com> <20241112161925.999196-4-christian.bruel@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20241112161925.999196-4-christian.bruel@foss.st.com> On Tue, Nov 12, 2024 at 05:19:23PM +0100, Christian Bruel wrote: > STM32MP25 PCIe Controller is based on the DesignWare core configured as > end point mode from the SYSCFG register. > > Signed-off-by: Christian Bruel > --- > .../bindings/pci/st,stm32-pcie-ep.yaml | 97 +++++++++++++++++++ > 1 file changed, 97 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/st,stm32-pcie-ep.yaml > > diff --git a/Documentation/devicetree/bindings/pci/st,stm32-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/st,stm32-pcie-ep.yaml > new file mode 100644 > index 000000000000..f0d215982794 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/st,stm32-pcie-ep.yaml > @@ -0,0 +1,97 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pci/st,stm32-pcie-ep.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: STM32MP25 PCIe endpoint driver > + > +maintainers: > + - Christian Bruel > + > +description: > + PCIe endpoint controller based on the Synopsys DesignWare PCIe core. > + > +allOf: > + - $ref: /schemas/pci/snps,dw-pcie-common.yaml# snps,dw-pcie-ep.yaml > + > +properties: > + compatible: > + const: st,stm32mp25-pcie-ep > + > + reg: > + items: > + - description: Data Bus Interface (DBI) registers. > + - description: PCIe configuration registers. > + > + reg-names: > + items: > + - const: dbi > + - const: addr_space > + > + clocks: > + maxItems: 1 > + description: PCIe system clock > + > + clock-names: > + const: core > + > + resets: > + maxItems: 1 > + > + reset-names: > + const: core > + > + phys: > + maxItems: 1 > + > + phy-names: > + const: pcie-phy > + > + reset-gpios: > + description: GPIO controlled connection to PERST# signal > + maxItems: 1 > + > + access-controllers: > + maxItems: 1 > + > + power-domains: > + maxItems: 1 All these properties common between RC and EP modes should be in a shared schema. > + > +required: > + - resets > + - reset-names > + - clocks > + - clock-names > + - phys > + - phy-names > + - reset-gpios > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + #include > + > + pcie-ep@48400000 { > + compatible = "st,stm32mp25-pcie-ep"; > + num-lanes = <1>; > + reg = <0x48400000 0x400000>, > + <0x10000000 0x8000000>; > + reg-names = "dbi", "addr_space"; > + clocks = <&rcc CK_BUS_PCIE>; > + clock-names = "core"; > + phys = <&combophy PHY_TYPE_PCIE>; > + phy-names = "pcie-phy"; > + resets = <&rcc PCIE_R>; > + reset-names = "core"; > + pinctrl-names = "default", "init"; > + pinctrl-0 = <&pcie_pins_a>; > + pinctrl-1 = <&pcie_init_pins_a>; > + reset-gpios = <&gpioj 8 GPIO_ACTIVE_LOW>; > + power-domains = <&CLUSTER_PD>; > + access-controllers = <&rifsc 68>; > + }; > -- > 2.34.1 >