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From: Marc Kleine-Budde <mkl@pengutronix.de>
To: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
Cc: Vincent Mailhol <mailhol.vincent@wanadoo.fr>,
	 Andrew Lunn <andrew+netdev@lunn.ch>,
	"David S . Miller" <davem@davemloft.net>,
	 Eric Dumazet <edumazet@google.com>,
	Jakub Kicinski <kuba@kernel.org>,
	 Paolo Abeni <pabeni@redhat.com>, Rob Herring <robh@kernel.org>,
	 Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	linux-can@vger.kernel.org,  netdev@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	 imx@lists.linux.dev, NXP Linux Team <s32@nxp.com>,
	 Christophe Lizzi <clizzi@redhat.com>,
	Alberto Ruiz <aruizrui@redhat.com>,
	 Enric Balletbo <eballetb@redhat.com>
Subject: Re: [PATCH 3/3] can: flexcan: handle S32G2/S32G3 separate interrupt lines
Date: Wed, 20 Nov 2024 12:33:40 +0100	[thread overview]
Message-ID: <20241120-spirited-vulture-of-coffee-423adb-mkl@pengutronix.de> (raw)
In-Reply-To: <06acdf7f-3b35-48bc-ab2e-9578221b7aea@oss.nxp.com>

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On 20.11.2024 13:02:56, Ciprian Marian Costea wrote:
> On 11/20/2024 12:54 PM, Marc Kleine-Budde wrote:
> > On 20.11.2024 12:47:02, Ciprian Marian Costea wrote:
> > > > > > > The mainline driver already handles the 2nd mailbox range (same
> > > > > > > 'flexcan_irq') is used. The only difference is that for the 2nd mailbox
> > > > > > > range a separate interrupt line is used.
> > > > > > 
> > > > > > AFAICS the IP core supports up to 128 mailboxes, though the driver only
> > > > > > supports 64 mailboxes. Which mailboxes do you mean by the "2nd mailbox
> > > > > > range"? What about mailboxes 64..127, which IRQ will them?
> > > > > 
> > > > > On S32G the following is the mapping between FlexCAN IRQs and mailboxes:
> > > > > - IRQ line X -> Mailboxes 0-7
> > > > > - IRQ line Y -> Mailboxes 8-127 (Logical OR of Message Buffer Interrupt
> > > > > lines 127 to 8)
> > > > > 
> > > > > By 2nd range, I was refering to Mailboxes 8-127.
> > > > 
> > > > Interesting, do you know why it's not symmetrical (0...63, 64...127)?
> > > > Can you point me to the documentation.
> > > 
> > > Unfortunately I do not know why such hardware integration decisions have
> > > been made.
> > > 
> > > Documentation for S32G3 SoC can be found on the official NXP website,
> > > here:
> > > https://www.nxp.com/products/processors-and-microcontrollers/s32-automotive-platform/s32g-vehicle-network-processors/s32g3-processors-for-vehicle-networking:S32G3
> > > 
> > > But please note that you need to setup an account beforehand.
> > 
> > I have that already, where is the mailbox to IRQ mapping described?
> > 
> > regards,
> > Marc
> > 
> 
> If you have successfully downloaded the Reference Manual for S32G2 or S32G3
> SoC, it should have attached an excel file describing all the interrupt
> mappings.

I downloaded the S32G3 Reference Manual:

| https://www.nxp.com/webapp/Download?colCode=RMS32G3

It's a pdf. Where can I find the execl file?

> In the excel file, if you search for 'FlexCAN_0' for example, you should be
> able to find IRQ lines 39 and 40 which correspond to Maiboxes 0-7 and 8-129
> (ored) previously discussed.

regards,
Marc

-- 
Pengutronix e.K.                 | Marc Kleine-Budde          |
Embedded Linux                   | https://www.pengutronix.de |
Vertretung Nürnberg              | Phone: +49-5121-206917-129 |
Amtsgericht Hildesheim, HRA 2686 | Fax:   +49-5121-206917-9   |

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  reply	other threads:[~2024-11-20 11:34 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-11-19  8:10 [PATCH 0/3] add FlexCAN support for S32G2/S32G3 SoCs Ciprian Costea
2024-11-19  8:10 ` [PATCH 1/3] dt-bindings: can: fsl,flexcan: add S32G2/S32G3 SoC support Ciprian Costea
2024-11-19 19:49   ` Frank Li
2024-11-20  8:45   ` Krzysztof Kozlowski
2024-11-20  9:12     ` Krzysztof Kozlowski
2024-11-20 10:33       ` Ciprian Marian Costea
2024-11-20  8:49   ` Marc Kleine-Budde
2024-11-20  9:04     ` Ciprian Marian Costea
2024-11-19  8:10 ` [PATCH 2/3] can: flexcan: add NXP " Ciprian Costea
2024-11-19 19:50   ` Frank Li
2024-11-20  9:01   ` Marc Kleine-Budde
2024-11-20  9:16     ` Ciprian Marian Costea
2024-11-19  8:10 ` [PATCH 3/3] can: flexcan: handle S32G2/S32G3 separate interrupt lines Ciprian Costea
2024-11-19  9:26   ` Vincent Mailhol
2024-11-19 10:01     ` Ciprian Marian Costea
2024-11-19 11:26       ` Vincent Mailhol
2024-11-19 11:28         ` Marc Kleine-Budde
2024-11-19 11:36         ` Vincent Mailhol
2024-11-19 11:40           ` Ciprian Marian Costea
2024-11-20  8:52   ` Marc Kleine-Budde
2024-11-20  9:01     ` Ciprian Marian Costea
2024-11-20 10:01       ` Marc Kleine-Budde
2024-11-20 10:18         ` Ciprian Marian Costea
2024-11-20 10:29           ` Marc Kleine-Budde
2024-11-20 10:47             ` Ciprian Marian Costea
2024-11-20 10:54               ` Marc Kleine-Budde
2024-11-20 11:02                 ` Ciprian Marian Costea
2024-11-20 11:33                   ` Marc Kleine-Budde [this message]
2024-11-20 11:42                     ` Ciprian Marian Costea

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