From: Andre Przywara <andre.przywara@arm.com>
To: Chen-Yu Tsai <wens@csie.org>
Cc: Linus Walleij <linus.walleij@linaro.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Samuel Holland <samuel@sholland.org>,
linux-gpio@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 5/7] dt-bindings: pinctrl: add compatible for Allwinner A523/T527
Date: Wed, 20 Nov 2024 10:12:28 +0000 [thread overview]
Message-ID: <20241120101228.26bbf100@donnerap.manchester.arm.com> (raw)
In-Reply-To: <CAGb2v64x_QE8w_4h10waG33xNpkd9QLt_B=xSPMMe0M=6bqsJw@mail.gmail.com>
On Wed, 13 Nov 2024 16:50:19 +0800
Chen-Yu Tsai <wens@csie.org> wrote:
Hi Chen-Yu,
sorry for the late reply, I was away for a week.
> On Mon, Nov 11, 2024 at 8:58 AM Andre Przywara <andre.przywara@arm.com> wrote:
> >
> > The A523 contains a pin controller similar to previous SoCs, although
> > using 10 GPIO banks (PortB-PortK), all of them being IRQ capable.
> > This introduces a new style of binding, where the pinmux values for each
> > pin group is stored in the new "allwinner,pinmux" property in the DT
> > node, instead of requiring every driver to store a mapping between the
> > function names and the required pinmux.
> >
> > Add the new name to the list of compatible strings, and required it to
> > have 10 interrupts described. Also add the new pinmux property.
> >
> > Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> > ---
> > .../pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 23 +++++++++++++++++--
> > 1 file changed, 21 insertions(+), 2 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
> > index 4502405703145..6fc18e92e1e94 100644
> > --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
> > +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
> > @@ -56,6 +56,8 @@ properties:
> > - allwinner,sun50i-h6-r-pinctrl
> > - allwinner,sun50i-h616-pinctrl
> > - allwinner,sun50i-h616-r-pinctrl
> > + - allwinner,sun55i-a523-pinctrl
> > + - allwinner,sun55i-a523-r-pinctrl
> > - allwinner,suniv-f1c100s-pinctrl
> > - nextthing,gr8-pinctrl
> >
> > @@ -64,7 +66,7 @@ properties:
> >
> > interrupts:
> > minItems: 1
> > - maxItems: 8
> > + maxItems: 10
> > description:
> > One interrupt per external interrupt bank supported on the
> > controller, sorted by bank number ascending order.
> > @@ -119,13 +121,17 @@ patternProperties:
> > $ref: /schemas/types.yaml#/definitions/uint32
> > enum: [10, 20, 30, 40]
> >
> > + allwinner,pinmux:
> > + $ref: /schemas/types.yaml#/definitions/uint32-array
> > + description: pinmux selector for each pin
> > +
>
> Why not just the standard "pinmux" property, as given in
> Documentation/devicetree/bindings/pinctrl/pinmux-node.yaml
I had it like this in my last post two years ago, but learned from
LinusW [1] that the generic pinmux property has a slightly different
meaning, and abusing it for just the pinmux index values would not match
the generic definition.
We *could* use the generic definition, but then this would include what's
in the "pins" property, like I sketched out in the cover letter, as an
alternative to this approach:
pinmux = <SUNXI_PIN(PB, 9, 2)>, <SUNXI_PIN(PB, 10, 2)>;
Where the SUNXI_PIN macro would combine the pin number and the pinmux into
one 32-bit cell. See the Apple GPIO DT nodes for an example.
This looks indeed nicer, but requires quite some rewrite of the existing
pinctrl driver, AFAICS.
[1] Previous reply from LinusW:
https://lore.kernel.org/linux-sunxi/CACRpkdbMc-Q6wjgsiddu6-tWC1dt2uFk+4LyerMdgFk2KRGK4w@mail.gmail.com/
>
> > required:
> > - pins
> > - function
>
> This section should be made to apply only to the existing
> compatibles? Maybe we could just split the files and have
> a clean slate for sun55i?
Yeah, I couldn't find a good example how to make it *required* for one
compatible and *not allowed* for all the others. But creating a whole new
file is actually a good idea, as this also avoids adding another case to
the already quite indented if-else cascade.
Cheers,
Andre
> ChenYu
>
> > additionalProperties: false
> >
> > - "^vcc-p[a-ilm]-supply$":
> > + "^vcc-p[a-klm]-supply$":
> > description:
> > Power supplies for pin banks.
> >
> > @@ -156,6 +162,17 @@ allOf:
> > - interrupts
> > - interrupt-controller
> >
> > + - if:
> > + properties:
> > + compatible:
> > + enum:
> > + - allwinner,sun55i-a523-pinctrl
> > +
> > + then:
> > + properties:
> > + interrupts:
> > + minItems: 10
> > +
> > - if:
> > properties:
> > compatible:
> > @@ -166,6 +183,7 @@ allOf:
> > properties:
> > interrupts:
> > minItems: 8
> > + maxItems: 8
> >
> > - if:
> > properties:
> > @@ -244,6 +262,7 @@ allOf:
> > - allwinner,sun8i-v3s-pinctrl
> > - allwinner,sun9i-a80-r-pinctrl
> > - allwinner,sun50i-h6-r-pinctrl
> > + - allwinner,sun55i-a523-r-pinctrl
> >
> > then:
> > properties:
> > --
> > 2.46.2
> >
next prev parent reply other threads:[~2024-11-20 10:12 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-11 0:57 [PATCH 0/7] pinctrl: sunxi: Add Allwinner A523 support Andre Przywara
2024-11-11 0:57 ` [PATCH 1/7] pinctrl: sunxi: refactor pinctrl variants into flags Andre Przywara
2024-11-11 0:57 ` [PATCH 2/7] pinctrl: sunxi: move bank K register offset Andre Przywara
2024-11-11 0:57 ` [PATCH 3/7] pinctrl: sunxi: support moved power configuration registers Andre Przywara
2024-11-11 0:57 ` [PATCH 4/7] pinctrl: sunxi: allow reading mux values from DT Andre Przywara
2024-11-11 0:57 ` [PATCH 5/7] dt-bindings: pinctrl: add compatible for Allwinner A523/T527 Andre Przywara
2024-11-12 15:38 ` Rob Herring
2024-11-13 8:50 ` Chen-Yu Tsai
2024-11-20 10:12 ` Andre Przywara [this message]
2024-11-11 0:57 ` [PATCH 6/7] pinctrl: sunxi: Add support for the Allwinner A523 Andre Przywara
2024-11-11 0:57 ` [PATCH 7/7] pinctrl: sunxi: Add support for the secondary A523 GPIO ports Andre Przywara
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