From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 09B5218FDC6; Sun, 24 Nov 2024 13:41:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732455672; cv=none; b=N+lLge8MRat1vBazse4YW/cl+mAMg8GVW/GM4WuB2DQ9Z5xqFVFrzq58fvwBGJOHTkGLKo5C7OWgwPm/HSj2syq9NxyDSJRD40pS/A4Yp/grjQpvvUCAdBM2HfE2Nr7u47iIQfIDdeDxp5RrOBuh8TgtQBFAYhi0PxCanll92u8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732455672; c=relaxed/simple; bh=TGY2yGGAe+1YXMUR63rNphBSEVUK/it2zX+cS+cyeiE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=W6liUiBWkD00fO94kT64tpTmm7mQ/ozdZ3+zQf9aYGVJVcUY1/3ULFlNEaBnSCuwzLkUxkpYQEczIKXd36OzJTLSd+XlQoO4+yQrj9HEQddDBp8wzVu52gOt02NBLZEV5gWgHB40K8PrbrKxlCxW2QUDySFuEJjyQ4IPCIpHSMU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=fbanAVrt; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="fbanAVrt" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B766EC4CED9; Sun, 24 Nov 2024 13:41:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1732455671; bh=TGY2yGGAe+1YXMUR63rNphBSEVUK/it2zX+cS+cyeiE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fbanAVrtVdsyKx3vfber2tyMwIXZZlJhu6eBpTyRVurLAKxSJKMZ8ooVYTokSlqvA X/XZrmTe6zKi1Pxqnh++6/44q4Xo1wFSUdeaBoIkcwHBpq2Q6c1rgRDG2y1MQXIJkY LgfqrLO0A/cSayA0b5BYmhkZ60uhBoX5NoeiyA0gWSENExTVvqi276+c1beB3l6rRz 9eUzZa55HdhRClCxRjbMQnj1jZqx1nWzF6Slyk7csxzssazKtFGB215au0NBEMl6dh kEiajpGAHCsfdFo50mi385fRQ2kNSfPnVqeIz3tIbnpz1FOZylSU6AWGXhiuSH9rOs zSMbYL4Op0Ltg== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Dave Stevenson , Maxime Ripard , Sasha Levin , maarten.lankhorst@linux.intel.com, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, dri-devel@lists.freedesktop.org Subject: [PATCH AUTOSEL 6.11 04/87] drm/vc4: hvs: Set AXI panic modes for the HVS Date: Sun, 24 Nov 2024 08:37:42 -0500 Message-ID: <20241124134102.3344326-4-sashal@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241124134102.3344326-1-sashal@kernel.org> References: <20241124134102.3344326-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 6.11.10 Content-Transfer-Encoding: 8bit From: Dave Stevenson [ Upstream commit 014eccc9da7bfc76a3107fceea37dd60f1d63630 ] The HVS can change AXI request mode based on how full the COB FIFOs are. Until now the vc4 driver has been relying on the firmware to have set these to sensible values. With HVS channel 2 now being used for live video, change the panic mode for all channels to be explicitly set by the driver, and the same for all channels. Reviewed-by: Maxime Ripard Link: https://patchwork.freedesktop.org/patch/msgid/20240621152055.4180873-7-dave.stevenson@raspberrypi.com Signed-off-by: Dave Stevenson Signed-off-by: Sasha Levin --- drivers/gpu/drm/vc4/vc4_hvs.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/vc4/vc4_hvs.c b/drivers/gpu/drm/vc4/vc4_hvs.c index 04af672caacb1..267c9fde7362d 100644 --- a/drivers/gpu/drm/vc4/vc4_hvs.c +++ b/drivers/gpu/drm/vc4/vc4_hvs.c @@ -951,6 +951,17 @@ static int vc4_hvs_bind(struct device *dev, struct device *master, void *data) SCALER_DISPCTRL_SCLEIRQ); + /* Set AXI panic mode. + * VC4 panics when < 2 lines in FIFO. + * VC5 panics when less than 1 line in the FIFO. + */ + dispctrl &= ~(SCALER_DISPCTRL_PANIC0_MASK | + SCALER_DISPCTRL_PANIC1_MASK | + SCALER_DISPCTRL_PANIC2_MASK); + dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC0); + dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC1); + dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC2); + /* Set AXI panic mode. * VC4 panics when < 2 lines in FIFO. * VC5 panics when less than 1 line in the FIFO. -- 2.43.0