From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B660A18FC75; Sun, 24 Nov 2024 13:41:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732455674; cv=none; b=NCLaIs6Xf1/ZDLEa34JlLGBjNPcs9Ftan6MFXaUXq/lgC++ub2qToeB1URMCeaSCGqAtwKN456R7n0hYpiMUY1izEQ2Vxgo1+c+fvgyucLipXWn8tfwlGShs5L/tTLSo103fr/J+cnQU6MaXlfqhV1sg6Q7PJj+uE+lvJ5c6D1o= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732455674; c=relaxed/simple; bh=yxb5R9btdU3CSmAv52EKtnc2EaHjs+udF4Mv8+W8DC0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=q1wgG1Q6m4kheKQRTIjnC9z7vPSuvvk4YoiXH7CvSi6bh6q5hLFGGeVCeZLSn2yEvNGq2bS+MUil6H84Jay0k6i8vVk1DHlhornEbKjB7RvynGCJHl9hciePZReLdBA6Qy6lf9B1+x1yApxsS9ovMG87oDuciBSRnpce2T2s178= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=RwyGO83D; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="RwyGO83D" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 59977C4CED9; Sun, 24 Nov 2024 13:41:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1732455673; bh=yxb5R9btdU3CSmAv52EKtnc2EaHjs+udF4Mv8+W8DC0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RwyGO83DQUyIdJCv5HPKsNSEdMwf36mL9XckJRaRvcIOrLqFKI5Uv8PvjSR1cM6Eo /6u9i2sX3m+6Q/ecEYL+fEpZwVBGMY8PaBLGizs/7bAqestPEirSVI8nqs688It+Pi /0RRvA9F8HcdxUEjHgNPQU3xaIGexXCl1i5Jz2nnTaIKPlD1b8tZ1WFOhF101ttSdu rqvq19wLX7MGP5qneXjUgRce8u0hMAWAgbvPZKjlLHVyuiC5duzmloZufiHOCR0bkN QqfDmGTMJOCRCkp2RAKCz6iQ8VDs1SthRvXc4cuCWbk8Y/j2Bf8785LudsFEa1+Rax EyugtYxuvl8Tg== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Dom Cobley , Maxime Ripard , Dave Stevenson , Sasha Levin , maarten.lankhorst@linux.intel.com, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, dri-devel@lists.freedesktop.org Subject: [PATCH AUTOSEL 6.11 05/87] drm/vc4: hdmi: Increase audio MAI fifo dreq threshold Date: Sun, 24 Nov 2024 08:37:43 -0500 Message-ID: <20241124134102.3344326-5-sashal@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241124134102.3344326-1-sashal@kernel.org> References: <20241124134102.3344326-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 6.11.10 Content-Transfer-Encoding: 8bit From: Dom Cobley [ Upstream commit 59f8b2b7fb8e460881d21c7d5b32604993973879 ] Now we wait for write responses and have a burst size of 4, we can set the fifo threshold much higher. Set it to 28 (of the 32 entry size) to keep fifo fuller and reduce chance of underflow. Signed-off-by: Dom Cobley Reviewed-by: Maxime Ripard Link: https://patchwork.freedesktop.org/patch/msgid/20240621152055.4180873-8-dave.stevenson@raspberrypi.com Signed-off-by: Dave Stevenson Signed-off-by: Sasha Levin --- drivers/gpu/drm/vc4/vc4_hdmi.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c index 5cb7ddec99a1f..0f0a58f814e9c 100644 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c @@ -2047,6 +2047,7 @@ static int vc4_hdmi_audio_prepare(struct device *dev, void *data, struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); struct drm_device *drm = vc4_hdmi->connector.dev; struct drm_connector *connector = &vc4_hdmi->connector; + struct vc4_dev *vc4 = to_vc4_dev(drm); unsigned int sample_rate = params->sample_rate; unsigned int channels = params->channels; unsigned long flags; @@ -2104,11 +2105,18 @@ static int vc4_hdmi_audio_prepare(struct device *dev, void *data, VC4_HDMI_AUDIO_PACKET_CEA_MASK); /* Set the MAI threshold */ - HDMI_WRITE(HDMI_MAI_THR, - VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICHIGH) | - VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICLOW) | - VC4_SET_FIELD(0x06, VC4_HD_MAI_THR_DREQHIGH) | - VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_DREQLOW)); + if (vc4->is_vc5) + HDMI_WRITE(HDMI_MAI_THR, + VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) | + VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) | + VC4_SET_FIELD(0x1c, VC4_HD_MAI_THR_DREQHIGH) | + VC4_SET_FIELD(0x1c, VC4_HD_MAI_THR_DREQLOW)); + else + HDMI_WRITE(HDMI_MAI_THR, + VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_PANICHIGH) | + VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_PANICLOW) | + VC4_SET_FIELD(0x6, VC4_HD_MAI_THR_DREQHIGH) | + VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_DREQLOW)); HDMI_WRITE(HDMI_MAI_CONFIG, VC4_HDMI_MAI_CONFIG_BIT_REVERSE | -- 2.43.0