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charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20241126-topic-sm8x50-pcie-global-irq-v1-1-4049cfccd073@linaro.org> On Tue, Nov 26, 2024 at 11:22:49AM +0100, Neil Armstrong wrote: > Qcom PCIe RC controllers are capable of generating 'global' SPI interrupt > to the host CPU. This interrupt can be used by the device driver to handle > PCIe link specific events such as Link up and Link down, which give the > driver a chance to start bus enumeration on its own when link is up and > initiate link training if link goes to a bad state. The PCIe driver can > still work without this interrupt but it will provide a nice user > experience when device gets plugged and removed. > > Document the interrupt as optional for SM8550 and SM8650 platforms. > > Signed-off-by: Neil Armstrong Acked-by: Manivannan Sadhasivam - Mani > --- > Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml | 9 ++++++--- > 1 file changed, 6 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml > index 24cb38673581d7391f877d3af5fadd6096c8d5be..19a614c74fa2aae94556ae3dfc24dcfcd520af11 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml > @@ -55,9 +55,10 @@ properties: > > interrupts: > minItems: 8 > - maxItems: 8 > + maxItems: 9 > > interrupt-names: > + minItems: 8 > items: > - const: msi0 > - const: msi1 > @@ -67,6 +68,7 @@ properties: > - const: msi5 > - const: msi6 > - const: msi7 > + - const: global > > resets: > minItems: 1 > @@ -137,9 +139,10 @@ examples: > , > , > , > - ; > + , > + ; > interrupt-names = "msi0", "msi1", "msi2", "msi3", > - "msi4", "msi5", "msi6", "msi7"; > + "msi4", "msi5", "msi6", "msi7", "global"; > #interrupt-cells = <1>; > interrupt-map-mask = <0 0 0 0x7>; > interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ > > -- > 2.34.1 > -- மணிவண்ணன் சதாசிவம்