[PATCH 0/4] renesas: r8a779g0: Enable VSPX on R-Car V4H

[PATCH 0/4] renesas: r8a779g0: Enable VSPX on R-Car V4H

[Jacopo Mondi]

The series enables the two VSPX instances connected to the R-Car ISP
on Renesas R-Car V4H. Define clock identifiers based on the MSTPCR id
for the VSPX instances and defined device nodes in the V4H .dts file.

The VSPX modules interface with extenal memory through dedicated FCP
instances named FCPVX. Before defining VSPDX, define and enable the
FXPVX instances as well.

Compile-tested only series.

Signed-off-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
---
Jacopo Mondi (4):
      clk: renesas: r8a779g0: Add FCPVX clocks
      arm64: dts: renesas: r8a779g0: Add FCPVX instances
      clk: renesas: r8a779g0: Add VSPX clocks
      arm64: dts: renesas: r8a779g0: Add VSPX instances

 arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 40 +++++++++++++++++++++++++++++++
 drivers/clk/renesas/r8a779g0-cpg-mssr.c   |  4 ++++
 2 files changed, 44 insertions(+)
---
base-commit: 50d451b19cc58cf374160e30cbf72a5ed5b1b129
change-id: 20241217-rcar-v4h-vspx-7d809b701c75

Best regards,
-- 
Jacopo Mondi <jacopo.mondi@ideasonboard.com>

[PATCH 1/4] clk: renesas: r8a779g0: Add FCPVX clocks

[Jacopo Mondi]

Add the FCPVX modules clock for Renesas R-Car V4H (R8A779G0) SoC.

Signed-off-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
---
 drivers/clk/renesas/r8a779g0-cpg-mssr.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
index 55c8dd032fc325c63727f21dc4d38b8e08ce0ca0..dc9ac2839ad9bb6c222db015de72fe8d9e7fe208 100644
--- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
@@ -238,6 +238,8 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
 	DEF_MOD("pfc2",		917,	R8A779G0_CLK_CP),
 	DEF_MOD("pfc3",		918,	R8A779G0_CLK_CP),
 	DEF_MOD("tsc",		919,	R8A779G0_CLK_CL16M),
+	DEF_MOD("fcpvx0",	1100,	R8A779G0_CLK_S0D4_VIO),
+	DEF_MOD("fcpvx1",	1101,	R8A779G0_CLK_S0D4_VIO),
 	DEF_MOD("tsn",		2723,	R8A779G0_CLK_S0D4_HSC),
 	DEF_MOD("ssiu",		2926,	R8A779G0_CLK_S0D6_PER),
 	DEF_MOD("ssi",		2927,	R8A779G0_CLK_S0D6_PER),

-- 
2.47.1

[PATCH 2/4] arm64: dts: renesas: r8a779g0: Add FCPVX instances

[Jacopo Mondi]

Add device nodes for the FCPVX instances on R-Car V4H (R8A779G0) SoC.

Signed-off-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
---
 arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
index 61c6b8022ffdc3b22444fb13e748b4aaebe454a4..e49748563e2f5706ed982d6c9cc1df59f27bd0dc 100644
--- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
@@ -2171,6 +2171,24 @@ fcpvd1: fcp@fea11000 {
 			iommus = <&ipmmu_vi1 7>;
 		};
 
+		fcpvx0: fcp@fedb0000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xfedb0000 0 0x200>;
+			clocks = <&cpg CPG_MOD 1100>;
+			power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+			resets = <&cpg 1100>;
+			iommus = <&ipmmu_vi1 24>;
+		};
+
+		fcpvx1: fcp@fedb8000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xfedb8000 0 0x200>;
+			clocks = <&cpg CPG_MOD 1101>;
+			power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+			resets = <&cpg 1101>;
+			iommus = <&ipmmu_vi1 25>;
+		};
+
 		vspd0: vsp@fea20000 {
 			compatible = "renesas,vsp2";
 			reg = <0 0xfea20000 0 0x7000>;

-- 
2.47.1

[PATCH 3/4] clk: renesas: r8a779g0: Add VSPX clocks

[Jacopo Mondi]

Add the VSPX modules clock for Renesas R-Car V4H (R8A779G0) SoC.

Signed-off-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
---
 drivers/clk/renesas/r8a779g0-cpg-mssr.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
index dc9ac2839ad9bb6c222db015de72fe8d9e7fe208..4e88096f8c4583d60debc3989fb22a51b41762a6 100644
--- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
@@ -238,6 +238,8 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
 	DEF_MOD("pfc2",		917,	R8A779G0_CLK_CP),
 	DEF_MOD("pfc3",		918,	R8A779G0_CLK_CP),
 	DEF_MOD("tsc",		919,	R8A779G0_CLK_CL16M),
+	DEF_MOD("vspx0",	1028,	R8A779G0_CLK_S0D4_VIO),
+	DEF_MOD("vspx1",	1029,	R8A779G0_CLK_S0D4_VIO),
 	DEF_MOD("fcpvx0",	1100,	R8A779G0_CLK_S0D4_VIO),
 	DEF_MOD("fcpvx1",	1101,	R8A779G0_CLK_S0D4_VIO),
 	DEF_MOD("tsn",		2723,	R8A779G0_CLK_S0D4_HSC),

-- 
2.47.1

[PATCH 4/4] arm64: dts: renesas: r8a779g0: Add VSPX instances

[Jacopo Mondi]

Add device nodes for the VSPX instances on R-Car V4H (R8A779G0) SoC.

Signed-off-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
---
 arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
index e49748563e2f5706ed982d6c9cc1df59f27bd0dc..bf4ec5fb7bbdba55e2994f332fcbd623839079c2 100644
--- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
@@ -2211,6 +2211,28 @@ vspd1: vsp@fea28000 {
 			renesas,fcp = <&fcpvd1>;
 		};
 
+		vspx0: vsp@fedd0000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xfedd0000 0 0x8000>;
+			interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 1028>;
+			power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+			resets = <&cpg 1028>;
+
+			renesas,fcp = <&fcpvx0>;
+		};
+
+		vspx1: vsp@fedd8000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xfedd8000 0 0x8000>;
+			interrupts = <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 1029>;
+			power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+			resets = <&cpg 1029>;
+
+			renesas,fcp = <&fcpvx1>;
+		};
+
 		du: display@feb00000 {
 			compatible = "renesas,du-r8a779g0";
 			reg = <0 0xfeb00000 0 0x40000>;

-- 
2.47.1

Re: [PATCH 2/4] arm64: dts: renesas: r8a779g0: Add FCPVX instances

[Laurent Pinchart]

Hi Jacopo,

Thank you for the patch.

On Tue, Dec 17, 2024 at 06:53:15PM +0100, Jacopo Mondi wrote:
> Add device nodes for the FCPVX instances on R-Car V4H (R8A779G0) SoC.
> 
> Signed-off-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
> ---
>  arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 18 ++++++++++++++++++
>  1 file changed, 18 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
> index 61c6b8022ffdc3b22444fb13e748b4aaebe454a4..e49748563e2f5706ed982d6c9cc1df59f27bd0dc 100644
> --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
> @@ -2171,6 +2171,24 @@ fcpvd1: fcp@fea11000 {
>  			iommus = <&ipmmu_vi1 7>;
>  		};
>  
> +		fcpvx0: fcp@fedb0000 {

Please sort the nodes by unit address.

Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

> +			compatible = "renesas,fcpv";
> +			reg = <0 0xfedb0000 0 0x200>;
> +			clocks = <&cpg CPG_MOD 1100>;
> +			power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
> +			resets = <&cpg 1100>;
> +			iommus = <&ipmmu_vi1 24>;
> +		};
> +
> +		fcpvx1: fcp@fedb8000 {
> +			compatible = "renesas,fcpv";
> +			reg = <0 0xfedb8000 0 0x200>;
> +			clocks = <&cpg CPG_MOD 1101>;
> +			power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
> +			resets = <&cpg 1101>;
> +			iommus = <&ipmmu_vi1 25>;
> +		};
> +
>  		vspd0: vsp@fea20000 {
>  			compatible = "renesas,vsp2";
>  			reg = <0 0xfea20000 0 0x7000>;

-- 
Regards,

Laurent Pinchart

Re: [PATCH 4/4] arm64: dts: renesas: r8a779g0: Add VSPX instances

[Laurent Pinchart]

Hi Jacopo,

Thank you for the patch.

On Tue, Dec 17, 2024 at 06:53:17PM +0100, Jacopo Mondi wrote:
> Add device nodes for the VSPX instances on R-Car V4H (R8A779G0) SoC.
> 
> Signed-off-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
> ---
>  arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
> index e49748563e2f5706ed982d6c9cc1df59f27bd0dc..bf4ec5fb7bbdba55e2994f332fcbd623839079c2 100644
> --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
> @@ -2211,6 +2211,28 @@ vspd1: vsp@fea28000 {
>  			renesas,fcp = <&fcpvd1>;
>  		};
>  
> +		vspx0: vsp@fedd0000 {

Please keep those sorted by unit address too.

> +			compatible = "renesas,vsp2";
> +			reg = <0 0xfedd0000 0 0x8000>;
> +			interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>;

The interrupts are listed as "negative level sensitive" in the
documentation. Tomi encountered a similar situation with the V4M VSP,
and setting the level to low in the DT didn't work. I assume this will
be fine, but if you encounter interrupt issues, this is one possible
area to investigate.

Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

> +			clocks = <&cpg CPG_MOD 1028>;
> +			power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
> +			resets = <&cpg 1028>;
> +
> +			renesas,fcp = <&fcpvx0>;
> +		};
> +
> +		vspx1: vsp@fedd8000 {
> +			compatible = "renesas,vsp2";
> +			reg = <0 0xfedd8000 0 0x8000>;
> +			interrupts = <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 1029>;
> +			power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
> +			resets = <&cpg 1029>;
> +
> +			renesas,fcp = <&fcpvx1>;
> +		};
> +
>  		du: display@feb00000 {
>  			compatible = "renesas,du-r8a779g0";
>  			reg = <0 0xfeb00000 0 0x40000>;

-- 
Regards,

Laurent Pinchart

Re: [PATCH 1/4] clk: renesas: r8a779g0: Add FCPVX clocks

[Laurent Pinchart]

Hi Jacopo,

Thank you for the patch.

On Tue, Dec 17, 2024 at 06:53:14PM +0100, Jacopo Mondi wrote:
> Add the FCPVX modules clock for Renesas R-Car V4H (R8A779G0) SoC.
> 
> Signed-off-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
> ---
>  drivers/clk/renesas/r8a779g0-cpg-mssr.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
> index 55c8dd032fc325c63727f21dc4d38b8e08ce0ca0..dc9ac2839ad9bb6c222db015de72fe8d9e7fe208 100644
> --- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
> @@ -238,6 +238,8 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
>  	DEF_MOD("pfc2",		917,	R8A779G0_CLK_CP),
>  	DEF_MOD("pfc3",		918,	R8A779G0_CLK_CP),
>  	DEF_MOD("tsc",		919,	R8A779G0_CLK_CL16M),
> +	DEF_MOD("fcpvx0",	1100,	R8A779G0_CLK_S0D4_VIO),
> +	DEF_MOD("fcpvx1",	1101,	R8A779G0_CLK_S0D4_VIO),

I can't really validate the parent as the documentation lists multiple
S0 clocks that driver the FCP, but this is one of them, so

Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

I expect that in reality the MSTP bit gates multiple clocks.

>  	DEF_MOD("tsn",		2723,	R8A779G0_CLK_S0D4_HSC),
>  	DEF_MOD("ssiu",		2926,	R8A779G0_CLK_S0D6_PER),
>  	DEF_MOD("ssi",		2927,	R8A779G0_CLK_S0D6_PER),

-- 
Regards,

Laurent Pinchart

Re: [PATCH 3/4] clk: renesas: r8a779g0: Add VSPX clocks

[Laurent Pinchart]

Hi Jacopo,

Thank you for the patch.

On Tue, Dec 17, 2024 at 06:53:16PM +0100, Jacopo Mondi wrote:
> Add the VSPX modules clock for Renesas R-Car V4H (R8A779G0) SoC.
> 
> Signed-off-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
> ---
>  drivers/clk/renesas/r8a779g0-cpg-mssr.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
> index dc9ac2839ad9bb6c222db015de72fe8d9e7fe208..4e88096f8c4583d60debc3989fb22a51b41762a6 100644
> --- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
> @@ -238,6 +238,8 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
>  	DEF_MOD("pfc2",		917,	R8A779G0_CLK_CP),
>  	DEF_MOD("pfc3",		918,	R8A779G0_CLK_CP),
>  	DEF_MOD("tsc",		919,	R8A779G0_CLK_CL16M),
> +	DEF_MOD("vspx0",	1028,	R8A779G0_CLK_S0D4_VIO),
> +	DEF_MOD("vspx1",	1029,	R8A779G0_CLK_S0D4_VIO),

Same comment about the parent as in 1/4.

Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

>  	DEF_MOD("fcpvx0",	1100,	R8A779G0_CLK_S0D4_VIO),
>  	DEF_MOD("fcpvx1",	1101,	R8A779G0_CLK_S0D4_VIO),
>  	DEF_MOD("tsn",		2723,	R8A779G0_CLK_S0D4_HSC),

-- 
Regards,

Laurent Pinchart

Re: [PATCH 4/4] arm64: dts: renesas: r8a779g0: Add VSPX instances

[Jacopo Mondi]

Hi Laurent

On Wed, Dec 18, 2024 at 01:42:15AM +0200, Laurent Pinchart wrote:
> Hi Jacopo,
>
> Thank you for the patch.
>
> On Tue, Dec 17, 2024 at 06:53:17PM +0100, Jacopo Mondi wrote:
> > Add device nodes for the VSPX instances on R-Car V4H (R8A779G0) SoC.
> >
> > Signed-off-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
> > ---
> >  arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 22 ++++++++++++++++++++++
> >  1 file changed, 22 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
> > index e49748563e2f5706ed982d6c9cc1df59f27bd0dc..bf4ec5fb7bbdba55e2994f332fcbd623839079c2 100644
> > --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
> > @@ -2211,6 +2211,28 @@ vspd1: vsp@fea28000 {
> >  			renesas,fcp = <&fcpvd1>;
> >  		};
> >
> > +		vspx0: vsp@fedd0000 {
>
> Please keep those sorted by unit address too.
>
> > +			compatible = "renesas,vsp2";
> > +			reg = <0 0xfedd0000 0 0x8000>;
> > +			interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>;
>
> The interrupts are listed as "negative level sensitive" in the
> documentation. Tomi encountered a similar situation with the V4M VSP,
> and setting the level to low in the DT didn't work. I assume this will
> be fine, but if you encounter interrupt issues, this is one possible
> area to investigate.

Yes, I noticed that the documentation says "negative", but I've done
the same here as it's done for the VSPD instances (which are equally
documented as negative), assuming that path had been tested.

>
> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Thanks
  j

>
> > +			clocks = <&cpg CPG_MOD 1028>;
> > +			power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
> > +			resets = <&cpg 1028>;
> > +
> > +			renesas,fcp = <&fcpvx0>;
> > +		};
> > +
> > +		vspx1: vsp@fedd8000 {
> > +			compatible = "renesas,vsp2";
> > +			reg = <0 0xfedd8000 0 0x8000>;
> > +			interrupts = <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>;
> > +			clocks = <&cpg CPG_MOD 1029>;
> > +			power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
> > +			resets = <&cpg 1029>;
> > +
> > +			renesas,fcp = <&fcpvx1>;
> > +		};
> > +
> >  		du: display@feb00000 {
> >  			compatible = "renesas,du-r8a779g0";
> >  			reg = <0 0xfeb00000 0 0x40000>;
>
> --
> Regards,
>
> Laurent Pinchart

Re: [PATCH 1/4] clk: renesas: r8a779g0: Add FCPVX clocks

[Jacopo Mondi]

Hi Laurent

On Wed, Dec 18, 2024 at 01:46:22AM +0200, Laurent Pinchart wrote:
> Hi Jacopo,
>
> Thank you for the patch.
>
> On Tue, Dec 17, 2024 at 06:53:14PM +0100, Jacopo Mondi wrote:
> > Add the FCPVX modules clock for Renesas R-Car V4H (R8A779G0) SoC.
> >
> > Signed-off-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
> > ---
> >  drivers/clk/renesas/r8a779g0-cpg-mssr.c | 2 ++
> >  1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
> > index 55c8dd032fc325c63727f21dc4d38b8e08ce0ca0..dc9ac2839ad9bb6c222db015de72fe8d9e7fe208 100644
> > --- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
> > +++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
> > @@ -238,6 +238,8 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
> >  	DEF_MOD("pfc2",		917,	R8A779G0_CLK_CP),
> >  	DEF_MOD("pfc3",		918,	R8A779G0_CLK_CP),
> >  	DEF_MOD("tsc",		919,	R8A779G0_CLK_CL16M),
> > +	DEF_MOD("fcpvx0",	1100,	R8A779G0_CLK_S0D4_VIO),
> > +	DEF_MOD("fcpvx1",	1101,	R8A779G0_CLK_S0D4_VIO),
>
> I can't really validate the parent as the documentation lists multiple
> S0 clocks that driver the FCP, but this is one of them, so

Here I decided to use the same clock as the VINs (200MHz)

However the ISPs clock parent is set to R8A779G0_CLK_S0D2_VIO (400MHz)
but that does not support the VSPX.

The only clock parent that can feed  [FCPVX, VSPX and ISP] is the
800MHz R8A779G0_CLK_S0D1_VIO parent.

>
> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
>
> I expect that in reality the MSTP bit gates multiple clocks.
>
> >  	DEF_MOD("tsn",		2723,	R8A779G0_CLK_S0D4_HSC),
> >  	DEF_MOD("ssiu",		2926,	R8A779G0_CLK_S0D6_PER),
> >  	DEF_MOD("ssi",		2927,	R8A779G0_CLK_S0D6_PER),
>
> --
> Regards,
>
> Laurent Pinchart