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From: Rik van Riel <riel@surriel.com>
To: x86@kernel.org
Cc: linux-kernel@vger.kernel.org, kernel-team@meta.com,
	dave.hansen@linux.intel.com, luto@kernel.org,
	peterz@infradead.org, tglx@linutronix.de, mingo@redhat.com,
	bp@alien8.de, hpa@zytor.com, akpm@linux-foundation.org,
	Rik van Riel <riel@surriel.com>
Subject: [PATCH 02/10] x86,tlb: get INVLPGB count max from CPUID
Date: Sat, 21 Dec 2024 23:06:34 -0500	[thread overview]
Message-ID: <20241222040717.3096835-3-riel@surriel.com> (raw)
In-Reply-To: <20241222040717.3096835-1-riel@surriel.com>

The CPU advertises the maximum number of pages that can be shot down
with one INVLPGB instruction in the CPUID data.

Save that information for later use.

Signed-off-by: Rik van Riel <riel@surriel.com>
---
 arch/x86/include/asm/processor.h | 2 ++
 arch/x86/kernel/cpu/amd.c        | 8 ++++++++
 2 files changed, 10 insertions(+)

diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 20e6009381ed..dd32a75d5da8 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -185,6 +185,8 @@ struct cpuinfo_x86 {
 	u16			booted_cores;
 	/* Index into per_cpu list: */
 	u16			cpu_index;
+	/* Max number of pages invalidated with one INVLPGB */
+	u16			invlpgb_count_max;
 	/*  Is SMT active on this core? */
 	bool			smt_active;
 	u32			microcode;
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 79d2e17f6582..6a6adbe9ae54 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -1135,6 +1135,14 @@ static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
 		tlb_lli_2m[ENTRIES] = eax & mask;
 
 	tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1;
+
+	if (c->extended_cpuid_level < 0x80000008)
+		return;
+
+	cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
+
+	/* Max number of pages INVLPGB can invalidate in one shot */
+	c->invlpgb_count_max = (edx & 0xffff) + 1;
 }
 
 static const struct cpu_dev amd_cpu_dev = {
-- 
2.47.1


  parent reply	other threads:[~2024-12-22  4:07 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-12-22  4:06 [RFC PATCH 00/10] AMD broadcast TLB invalidation Rik van Riel
2024-12-22  4:06 ` [PATCH 01/10] Add X86_FEATURE_INVLPGB definition Rik van Riel
2024-12-22  4:06 ` Rik van Riel [this message]
2024-12-22 11:46   ` [PATCH 02/10] x86,tlb: get INVLPGB count max from CPUID Borislav Petkov
2024-12-22 14:39     ` Rik van Riel
2024-12-22  4:06 ` [PATCH 03/10] x86,mm: add INVLPGB support code Rik van Riel
2024-12-22 11:05   ` Peter Zijlstra
2024-12-22 21:24     ` Rik van Riel
2024-12-22  4:06 ` [PATCH 04/10] x86,mm: use INVLPGB for kernel TLB flushes Rik van Riel
2024-12-22 11:16   ` Peter Zijlstra
2024-12-22 15:12     ` Rik van Riel
2024-12-24 18:13       ` Peter Zijlstra
2024-12-22 11:47   ` Borislav Petkov
2024-12-22  4:06 ` [PATCH 05/10] x86,tlb: use INVLPGB in flush_tlb_all Rik van Riel
2024-12-22 11:17   ` Peter Zijlstra
2024-12-22  4:06 ` [PATCH 06/10] x86,mm: use broadcast TLB flushing for page reclaim TLB flushing Rik van Riel
2024-12-22 11:18   ` Peter Zijlstra
2024-12-22  4:06 ` [PATCH 07/10] x86,mm: enable broadcast TLB invalidation for multi-threaded processes Rik van Riel
2024-12-22 11:36   ` Peter Zijlstra
2024-12-22 22:45     ` Rik van Riel
2024-12-22  4:06 ` [PATCH 08/10] x86,tlb: do targeted broadcast flushing from tlbbatch code Rik van Riel
2024-12-22  4:06 ` [PATCH 09/10] x86/mm: enable AMD translation cache extensions Rik van Riel
2024-12-22 11:38   ` Peter Zijlstra
2024-12-22 15:37     ` Rik van Riel
2024-12-24 18:25       ` Peter Zijlstra
2024-12-22  4:06 ` [PATCH 10/10] x86/mm: only invalidate final translations with INVLPGB Rik van Riel
2024-12-22 11:11 ` [RFC PATCH 00/10] AMD broadcast TLB invalidation Peter Zijlstra
2024-12-22 15:06   ` Rik van Riel

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