From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from shelob.surriel.com (shelob.surriel.com [96.67.55.147]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B3F26130A54 for ; Sun, 22 Dec 2024 04:07:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=96.67.55.147 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734840477; cv=none; b=V+mUoubmTMaGZvilh6VbRXueMePUBGkai0Wvq/mTqJSgwTWgZNfzmcvWN3+HUV3R3bZuExp8+vMt2CXQhIP/mgNm7DT/8mJRKnd1q4RY33sgJhfwNyTgR1SSZn3gTyzy4eXvdYApj6/MnRXQh1ARa94GPgyxeQ+dia52X5se9yY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734840477; c=relaxed/simple; bh=jOmKUFFzldSM1gAi1MplufQceBwyNFJ122fYDxvlMuc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=RCj9CxQ3U7Ov+JWciCeVoXp00mTLVKzqlk65havhWb0nphJ+17gxhIfAzJPL4zK8MQb4KOGP3rDRDLiaa0o4oBYWZBi0oS4nxkfItNCQNMLBo3mTDQZr7WkiAuPz36Y1kwprvccE9YQhwMClR2PFMHkvUO5br3tZKqtR2Y6WGc4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com; spf=pass smtp.mailfrom=shelob.surriel.com; arc=none smtp.client-ip=96.67.55.147 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=shelob.surriel.com Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tPDFT-000000000V0-1Y6X; Sat, 21 Dec 2024 23:07:23 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@meta.com, dave.hansen@linux.intel.com, luto@kernel.org, peterz@infradead.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, akpm@linux-foundation.org, Rik van Riel Subject: [PATCH 03/10] x86,mm: add INVLPGB support code Date: Sat, 21 Dec 2024 23:06:35 -0500 Message-ID: <20241222040717.3096835-4-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241222040717.3096835-1-riel@surriel.com> References: <20241222040717.3096835-1-riel@surriel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: riel@surriel.com Add invlpgb.h with the helper functions and definitions needed to use broadcast TLB invalidation on AMD EPYC 3 and newer CPUs. Signed-off-by: Rik van Riel --- arch/x86/include/asm/invlpgb.h | 98 +++++++++++++++++++++++++++++++++ arch/x86/include/asm/tlbflush.h | 1 + 2 files changed, 99 insertions(+) create mode 100644 arch/x86/include/asm/invlpgb.h diff --git a/arch/x86/include/asm/invlpgb.h b/arch/x86/include/asm/invlpgb.h new file mode 100644 index 000000000000..ef12ea4a8d65 --- /dev/null +++ b/arch/x86/include/asm/invlpgb.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_X86_INVLPGB +#define _ASM_X86_INVLPGB + +#include + +/* + * INVLPGB does broadcast TLB invalidation across all the CPUs in the system. + * + * The INVLPGB instruction is weakly ordered, and a batch of invalidations can be done in + * a parallel fashion. + * + * TLBSYNC is used to ensure that pending INVLPGB invalidations initiated from this CPU + * have completed. + */ +static inline void __invlpgb(unsigned long asid, unsigned long pcid, unsigned long addr, + int extra_count, bool pmd_stride, unsigned long flags) +{ + u64 rax = addr | flags; + u32 ecx = (pmd_stride << 31) | extra_count; + u32 edx = (pcid << 16) | asid; + + /* + * The memory clobber is because the whole point is to invalidate + * stale TLB entries and, especially if we're flushing global + * mappings, we don't want the compiler to reorder any subsequent + * memory accesses before the TLB flush. + */ + asm volatile("invlpgb" : : "a" (rax), "c" (ecx), "d" (edx)); +} + +/* + * INVLPGB can be targeted by virtual address, PCID, ASID, or any combination of the + * three. For example: + * - INVLPGB_VA | INVLPGB_INCLUDE_GLOBAL: invalidate all TLB entries at the address + * - INVLPGB_PCID: invalidate all TLB entries matching the PCID + * - INVLPGB_VA | INVLPGB_ASID: invalidate TLB entries matching the address & ASID + * + * The first can be used to invalidate kernel mappings across all processes. + * The last can be used to invalidate mappings across both PCIDs of a process when using PTI. + */ +#define INVLPGB_VA BIT(0) +#define INVLPGB_PCID BIT(1) +#define INVLPGB_ASID BIT(2) +#define INVLPGB_INCLUDE_GLOBAL BIT(3) +#define INVLPGB_FINAL_ONLY BIT(4) +#define INVLPGB_INCLUDE_NESTED BIT(5) + +/* Flush all mappings for a given pcid and addr, not including globals. */ +static inline void invlpgb_flush_user(unsigned long pcid, + unsigned long addr) +{ + __invlpgb(0, pcid, addr, 0, 0, INVLPGB_PCID | INVLPGB_VA); +} + +static inline void invlpgb_flush_user_nr(unsigned long pcid, unsigned long addr, int nr, + bool pmd_stride) +{ + __invlpgb(0, pcid, addr, nr - 1, pmd_stride, INVLPGB_PCID | INVLPGB_VA); +} + +/* Flush all mappings for a given ASID, not including globals. */ +static inline void invlpgb_flush_single_asid(unsigned long asid) +{ + __invlpgb(asid, 0, 0, 0, 0, INVLPGB_ASID); +} + +/* Flush all mappings for a given PCID, not including globals. */ +static inline void invlpgb_flush_single_pcid(unsigned long pcid) +{ + __invlpgb(0, pcid, 0, 0, 0, INVLPGB_PCID); +} + +/* Flush all mappings, including globals, for all PCIDs. */ +static inline void invlpgb_flush_all(void) +{ + __invlpgb(0, 0, 0, 0, 0, INVLPGB_INCLUDE_GLOBAL); +} + +/* Flush addr, including globals, for all PCIDs. */ +static inline void invlpgb_flush_addr(unsigned long addr, int nr) +{ + __invlpgb(0, 0, addr, nr - 1, 0, INVLPGB_INCLUDE_GLOBAL); +} + +/* Flush all mappings for all PCIDs except globals. */ +static inline void invlpgb_flush_all_nonglobals(void) +{ + __invlpgb(0, 0, 0, 0, 0, 0); +} + +/* Wait for INVLPGB originated by this CPU to complete. */ +static inline void tlbsync(void) +{ + asm volatile("tlbsync"); +} + +#endif /* _ASM_X86_INVLPGB */ diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h index 02fc2aa06e9e..1f518fb9abba 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include -- 2.47.1