From: Peter Zijlstra <peterz@infradead.org>
To: Rik van Riel <riel@surriel.com>
Cc: x86@kernel.org, linux-kernel@vger.kernel.org,
kernel-team@meta.com, dave.hansen@linux.intel.com,
luto@kernel.org, tglx@linutronix.de, mingo@redhat.com,
bp@alien8.de, hpa@zytor.com, akpm@linux-foundation.org
Subject: Re: [PATCH 09/10] x86/mm: enable AMD translation cache extensions
Date: Sun, 22 Dec 2024 12:38:11 +0100 [thread overview]
Message-ID: <20241222113811.GY11133@noisy.programming.kicks-ass.net> (raw)
In-Reply-To: <20241222040717.3096835-10-riel@surriel.com>
On Sat, Dec 21, 2024 at 11:06:41PM -0500, Rik van Riel wrote:
> With AMD TCE (translation cache extensions) only the intermediate mappings
Only the leave mapings, as written this all don't make sense,
> that cover the address range zapped by INVLPG / INVLPGB get invalidated,
> rather than all intermediate mappings getting zapped at every TLB invalidation.
>
> This can help reduce the TLB miss rate, by keeping more intermediate
> mappings in the cache.
next prev parent reply other threads:[~2024-12-22 11:38 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-22 4:06 [RFC PATCH 00/10] AMD broadcast TLB invalidation Rik van Riel
2024-12-22 4:06 ` [PATCH 01/10] Add X86_FEATURE_INVLPGB definition Rik van Riel
2024-12-22 4:06 ` [PATCH 02/10] x86,tlb: get INVLPGB count max from CPUID Rik van Riel
2024-12-22 11:46 ` Borislav Petkov
2024-12-22 14:39 ` Rik van Riel
2024-12-22 4:06 ` [PATCH 03/10] x86,mm: add INVLPGB support code Rik van Riel
2024-12-22 11:05 ` Peter Zijlstra
2024-12-22 21:24 ` Rik van Riel
2024-12-22 4:06 ` [PATCH 04/10] x86,mm: use INVLPGB for kernel TLB flushes Rik van Riel
2024-12-22 11:16 ` Peter Zijlstra
2024-12-22 15:12 ` Rik van Riel
2024-12-24 18:13 ` Peter Zijlstra
2024-12-22 11:47 ` Borislav Petkov
2024-12-22 4:06 ` [PATCH 05/10] x86,tlb: use INVLPGB in flush_tlb_all Rik van Riel
2024-12-22 11:17 ` Peter Zijlstra
2024-12-22 4:06 ` [PATCH 06/10] x86,mm: use broadcast TLB flushing for page reclaim TLB flushing Rik van Riel
2024-12-22 11:18 ` Peter Zijlstra
2024-12-22 4:06 ` [PATCH 07/10] x86,mm: enable broadcast TLB invalidation for multi-threaded processes Rik van Riel
2024-12-22 11:36 ` Peter Zijlstra
2024-12-22 22:45 ` Rik van Riel
2024-12-22 4:06 ` [PATCH 08/10] x86,tlb: do targeted broadcast flushing from tlbbatch code Rik van Riel
2024-12-22 4:06 ` [PATCH 09/10] x86/mm: enable AMD translation cache extensions Rik van Riel
2024-12-22 11:38 ` Peter Zijlstra [this message]
2024-12-22 15:37 ` Rik van Riel
2024-12-24 18:25 ` Peter Zijlstra
2024-12-22 4:06 ` [PATCH 10/10] x86/mm: only invalidate final translations with INVLPGB Rik van Riel
2024-12-22 11:11 ` [RFC PATCH 00/10] AMD broadcast TLB invalidation Peter Zijlstra
2024-12-22 15:06 ` Rik van Riel
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