From: "Heiko Stübner" <heiko@sntech.de>
To: "Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Oded Gabbay" <ogabbay@kernel.org>,
"Jonathan Corbet" <corbet@lwn.net>,
"Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
"Maxime Ripard" <mripard@kernel.org>,
"Thomas Zimmermann" <tzimmermann@suse.de>,
"David Airlie" <airlied@gmail.com>,
"Simona Vetter" <simona@ffwll.ch>,
"Sumit Semwal" <sumit.semwal@linaro.org>,
"Christian König" <christian.koenig@amd.com>,
"Sebastian Reichel" <sebastian.reichel@collabora.com>,
"Nicolas Frattaroli" <nicolas.frattaroli@collabora.com>,
"Kever Yang" <kever.yang@rock-chips.com>,
"Jeff Hugo" <jeff.hugo@oss.qualcomm.com>,
"Tomeu Vizoso" <tomeu@tomeuvizoso.net>
Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
dri-devel@lists.freedesktop.org, linux-doc@vger.kernel.org,
linux-media@vger.kernel.org, linaro-mm-sig@lists.linaro.org,
Tomeu Vizoso <tomeu@tomeuvizoso.net>,
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Subject: Re: [PATCH v6 01/10] dt-bindings: npu: rockchip,rknn: Add bindings
Date: Wed, 04 Jun 2025 10:25:20 +0200 [thread overview]
Message-ID: <2024813.jZfb76A358@diego> (raw)
In-Reply-To: <20250604-6-10-rocket-v6-1-237ac75ddb5e@tomeuvizoso.net>
Am Mittwoch, 4. Juni 2025, 09:57:14 Mitteleuropäische Sommerzeit schrieb Tomeu Vizoso:
> Add the bindings for the Neural Processing Unit IP from Rockchip.
>
> v2:
> - Adapt to new node structure (one node per core, each with its own
> IOMMU)
> - Several misc. fixes from Sebastian Reichel
>
> v3:
> - Split register block in its constituent subblocks, and only require
> the ones that the kernel would ever use (Nicolas Frattaroli)
> - Group supplies (Rob Herring)
> - Explain the way in which the top core is special (Rob Herring)
>
> v4:
> - Change required node name to npu@ (Rob Herring and Krzysztof Kozlowski)
> - Remove unneeded items: (Krzysztof Kozlowski)
> - Fix use of minItems/maxItems (Krzysztof Kozlowski)
> - Add reg-names to list of required properties (Krzysztof Kozlowski)
> - Fix example (Krzysztof Kozlowski)
>
> v5:
> - Rename file to rockchip,rk3588-rknn-core.yaml (Krzysztof Kozlowski)
> - Streamline compatible property (Krzysztof Kozlowski)
>
> v6:
> - Remove mention to NVDLA, as the hardware is only incidentally related
> (Kever Yang)
> - Mark pclk and npu clocks as required by all clocks (Rob Herring)
>
> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
> Signed-off-by: Tomeu Vizoso <tomeu@tomeuvizoso.net>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
> .../bindings/npu/rockchip,rk3588-rknn-core.yaml | 144 +++++++++++++++++++++
> 1 file changed, 144 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..9a5e9e213912d0997da2f6ae26189adf044dcc7b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml
> @@ -0,0 +1,144 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/npu/rockchip,rk3588-rknn-core.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Neural Processing Unit IP from Rockchip
> +
> +maintainers:
> + - Tomeu Vizoso <tomeu@tomeuvizoso.net>
> +
> +description:
> + Rockchip IP for accelerating inference of neural networks.
> +
> + There is to be a node per each core in the NPU. In Rockchip's design there
> + will be one core that is special and needs to be powered on before any of the
> + other cores can be used. This special core is called the top core and should
> + have the compatible string that corresponds to top cores.
> +
> +properties:
> + $nodename:
> + pattern: '^npu@[a-f0-9]+$'
> +
> + compatible:
> + enum:
> + - rockchip,rk3588-rknn-core-top
> + - rockchip,rk3588-rknn-core
> +
> + reg:
> + maxItems: 3
> +
> + reg-names:
> + items:
> + - const: pc
> + - const: cna
> + - const: core
> +
> + clocks:
> + maxItems: 4
> +
> + clock-names:
> + items:
> + - const: aclk
> + - const: hclk
> + - const: npu
> + - const: pclk
> +
> + interrupts:
> + maxItems: 1
> +
> + iommus:
> + maxItems: 1
> +
> + npu-supply: true
> +
> + power-domains:
> + maxItems: 1
> +
> + resets:
> + maxItems: 2
> +
> + reset-names:
> + items:
> + - const: srst_a
> + - const: srst_h
> +
> + sram-supply: true
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - clocks
> + - clock-names
> + - interrupts
> + - iommus
> + - power-domains
> + - resets
> + - reset-names
> + - npu-supply
> + - sram-supply
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - rockchip,rknn-core-top
should be rockchip,rk3588-rknn-core-top I think
> + then:
> + properties:
> + clocks:
> + minItems: 4
> +
> + clock-names:
> + minItems: 4
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - rockchip,rknn-core
should be rockchip,rk3588-rknn-core
> + then:
> + properties:
> + clocks:
> + maxItems: 2
> + clock-names:
> + maxItems: 2
Heiko
next prev parent reply other threads:[~2025-06-04 8:26 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-04 7:57 [PATCH v6 00/10] New DRM accel driver for Rockchip's RKNN NPU Tomeu Vizoso
2025-06-04 7:57 ` [PATCH v6 01/10] dt-bindings: npu: rockchip,rknn: Add bindings Tomeu Vizoso
2025-06-04 8:25 ` Heiko Stübner [this message]
2025-06-04 8:36 ` Tomeu Vizoso
2025-06-04 7:57 ` [PATCH v6 02/10] arm64: dts: rockchip: Add nodes for NPU and its MMU to rk3588-base Tomeu Vizoso
2025-06-04 7:57 ` [PATCH v6 03/10] arm64: dts: rockchip: Enable the NPU on quartzpro64 Tomeu Vizoso
2025-06-04 8:39 ` Heiko Stübner
2025-06-04 7:57 ` [PATCH v6 04/10] accel/rocket: Add registers header Tomeu Vizoso
2025-06-04 7:57 ` [PATCH v6 05/10] accel/rocket: Add a new driver for Rockchip's NPU Tomeu Vizoso
2025-06-04 18:14 ` Robin Murphy
2025-06-04 7:57 ` [PATCH v6 06/10] accel/rocket: Add IOCTL for BO creation Tomeu Vizoso
2025-06-04 16:18 ` Daniel Stone
2025-06-04 17:03 ` Robin Murphy
2025-06-05 7:41 ` Tomeu Vizoso
2025-06-05 12:29 ` Daniel Stone
2025-06-05 12:57 ` Tomeu Vizoso
2025-06-05 13:37 ` Robin Murphy
2025-06-05 16:32 ` Tomeu Vizoso
2025-06-05 16:36 ` Daniel Stone
2025-06-04 7:57 ` [PATCH v6 07/10] accel/rocket: Add job submission IOCTL Tomeu Vizoso
2025-06-04 7:57 ` [PATCH v6 08/10] accel/rocket: Add IOCTLs for synchronizing memory accesses Tomeu Vizoso
2025-06-04 7:57 ` [PATCH v6 09/10] arm64: dts: rockchip: add pd_npu label for RK3588 power domains Tomeu Vizoso
2025-06-04 7:57 ` [PATCH v6 10/10] arm64: dts: rockchip: enable NPU on ROCK 5B Tomeu Vizoso
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