RE: [PATCH v2] arm64: dts: add cpu cache information to ExynosAuto-v920

Alim Akhtar
2025-02-05T16:07:16Z

Hi Sudeep

> -----Original Message-----
> From: Sudeep Holla <sudeep.holla@arm.com>
> Sent: Friday, January 31, 2025 6:57 PM
> To: Alim Akhtar <alim.akhtar@samsung.com>
> Cc: 'Devang Tailor' <dev.tailor@samsung.com>; robh@kernel.org;
> krzk+dt@kernel.org; conor+dt@kernel.org; devicetree@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; linux-samsung-soc@vger.kernel.org;
> linux-kernel@vger.kernel.org; faraz.ata@samsung.com
> Subject: Re: [PATCH v2] arm64: dts: add cpu cache information to
> ExynosAuto-v920
>
[snip]
> > You can add one node for cl0 and cl1, say "l3_cache_cl0_cl1" and
> > Remove the specific node for CL1, because both are same.
> >
>
> What do you mean by "both are same" ?
> Do you mean both have exact same properties but are physically different
> caches ? OR Do you mean it is just one shared cache ?
>
Thanks for review and pointing it out, v920 has physically different caches
(two of them are same properties, but the 3rd has 1MB lesser size)
Got you point about having distinct node for cacheinfo population
So for this patch:

Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>

> If former, we still need distinct node to get the cacheinfo about
shareability
> correct. If this is about avoiding duplication of errors, you can probably
define
> some macro and avoid it, but we need 2 nodes in the devicetree.
>
> If latter, you suggestion is correct.
>
> --
> Regards,
> Sudeep