From: kernel test robot <lkp@intel.com>
To: Yushan Wang <wangyushan12@huawei.com>,
xuwei5@hisilicon.com, yangyicong@hisilicon.com,
Jonathan.Cameron@huawei.com, wangjie125@huawei.com,
linux-kernel@vger.kernel.org
Cc: llvm@lists.linux.dev, oe-kbuild-all@lists.linux.dev,
prime.zeng@hisilicon.com, fanghao11@huawei.com,
wangyushan12@huawei.com, linuxarm@huawei.com
Subject: Re: [PATCH 2/2] soc cache: L3 cache lockdown support for HiSilicon SoC
Date: Wed, 8 Jan 2025 22:37:08 +0800 [thread overview]
Message-ID: <202501082259.J9fBJZTQ-lkp@intel.com> (raw)
In-Reply-To: <20250107132907.3521574-3-wangyushan12@huawei.com>
Hi Yushan,
kernel test robot noticed the following build warnings:
[auto build test WARNING on linus/master]
[also build test WARNING on v6.13-rc6 next-20250108]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Yushan-Wang/soc-cache-Add-framework-driver-for-HiSilicon-SoC-cache/20250107-213022
base: linus/master
patch link: https://lore.kernel.org/r/20250107132907.3521574-3-wangyushan12%40huawei.com
patch subject: [PATCH 2/2] soc cache: L3 cache lockdown support for HiSilicon SoC
config: arm64-allmodconfig (https://download.01.org/0day-ci/archive/20250108/202501082259.J9fBJZTQ-lkp@intel.com/config)
compiler: clang version 18.1.8 (https://github.com/llvm/llvm-project 3b5b5c1ec4a3095ab096dd780e84d7ab81f3d7ff)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250108/202501082259.J9fBJZTQ-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202501082259.J9fBJZTQ-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> drivers/soc/hisilicon/hisi_soc_l3c.c:146: warning: Function parameter or struct member 'regset' not described in 'hisi_soc_l3c_free_lock_reg_set'
>> drivers/soc/hisilicon/hisi_soc_l3c.c:146: warning: Excess function parameter 'addr' description in 'hisi_soc_l3c_free_lock_reg_set'
vim +146 drivers/soc/hisilicon/hisi_soc_l3c.c
136
137 /**
138 * hisi_soc_l3c_free_lock_reg_set - Free an allocated register set by locked
139 * address.
140 *
141 * @soc_l3c: The L3C instance on which the register set is allocated.
142 * @addr: The locked address.
143 */
144 static void hisi_soc_l3c_free_lock_reg_set(struct hisi_soc_l3c *soc_l3c,
145 int regset)
> 146 {
147 if (regset < 0)
148 return;
149
150 xa_erase(&soc_l3c->lock_sets, regset);
151 }
152
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
next prev parent reply other threads:[~2025-01-08 14:37 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-07 13:29 [PATCH 0/2] soc cache: Add support for HiSilicon L3 cache Yushan Wang
2025-01-07 13:29 ` [PATCH 1/2] soc cache: Add framework driver for HiSilicon SoC cache Yushan Wang
2025-01-07 19:05 ` Christophe JAILLET
2025-01-08 9:59 ` wangyushan
2025-01-08 13:54 ` kernel test robot
2025-01-07 13:29 ` [PATCH 2/2] soc cache: L3 cache lockdown support for HiSilicon SoC Yushan Wang
2025-01-08 14:37 ` kernel test robot [this message]
2025-01-08 15:32 ` kernel test robot
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