Re: [PATCH v3 3/5] arm64: dts: agilex: add dtsi for PCIe Root Port

matthew.gerlach
2025-01-08T22:53:55Z

On Wed, 8 Jan 2025, Bjorn Helgaas wrote:

> On Wed, Jan 08, 2025 at 10:59:07AM -0600, Matthew Gerlach wrote:
>> Add the base device tree for support of the PCIe Root Port
>> for the Agilex family of chips.
>>
>> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
>> ---
>> v3:
>> - Remove accepted patches from patch set.
>>
>> v2:
>> - Rename node to fix schema check error.
>> ---
>> .../intel/socfpga_agilex_pcie_root_port.dtsi | 55 +++++++++++++++++++
>> 1 file changed, 55 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi
>> new file mode 100644
>> index 000000000000..50f131f5791b
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi
>> @@ -0,0 +1,55 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2024, Intel Corporation
>> + */
>> +&soc0 {
>> + aglx_hps_bridges: fpga-bus@80000000 {
>> + compatible = "simple-bus";
>> + reg = <0x80000000 0x20200000>,
>> + <0xf9000000 0x00100000>;
>> + reg-names = "axi_h2f", "axi_h2f_lw";
>> + #address-cells = <0x2>;
>> + #size-cells = <0x1>;
>> + ranges = <0x00000000 0x00000000 0x80000000 0x00040000>,
>> + <0x00000000 0x10000000 0x90100000 0x0ff00000>,
>> + <0x00000000 0x20000000 0xa0000000 0x00200000>,
>> + <0x00000001 0x00010000 0xf9010000 0x00008000>,
>> + <0x00000001 0x00018000 0xf9018000 0x00000080>,
>> + <0x00000001 0x00018080 0xf9018080 0x00000010>;
>> +
>> + pcie_0_pcie_aglx: pcie@200000000 {
>> + reg = <0x00000000 0x10000000 0x10000000>,
>> + <0x00000001 0x00010000 0x00008000>,
>> + <0x00000000 0x20000000 0x00200000>;
>> + reg-names = "Txs", "Cra", "Hip";
>> + interrupt-parent = <&intc>;
>> + interrupts = <GIC_SPI 0x14 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-controller;
>> + #interrupt-cells = <0x1>;
>> + device_type = "pci";
>> + bus-range = <0x0000000 0x000000ff>;
>
> I don't think this bus-range is needed since
> pci_parse_request_of_pci_ranges() defaults to 00-ff when bus-range is
> absent.
>

Yes, pci_parse_request_of_pci_ranges() does default to using 00-ff when
the bus-range property is absent. Removing the bus-range property does
result in an extra kernel message at startup:
No bus range found for ...,using [bus 00-ff].

If the extra kernel message is not a problem, then removing the bus-range
property does result in a smaller device tree.

Matthew Gerlach