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From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
To: Robert Richter <rrichter@amd.com>
Cc: Alison Schofield <alison.schofield@intel.com>,
	Vishal Verma <vishal.l.verma@intel.com>,
	Ira Weiny <ira.weiny@intel.com>,
	Dan Williams <dan.j.williams@intel.com>,
	Dave Jiang <dave.jiang@intel.com>,
	"Davidlohr Bueso" <dave@stgolabs.net>,
	<linux-cxl@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	Gregory Price <gourry@gourry.net>,
	"Fabio M. De Francesco" <fabio.m.de.francesco@linux.intel.com>,
	Terry Bowman <terry.bowman@amd.com>
Subject: Re: [PATCH v1 05/29] cxl/region: Move find_cxl_root() to cxl_add_to_region()
Date: Mon, 13 Jan 2025 16:52:33 +0000	[thread overview]
Message-ID: <20250113165233.000067e3@huawei.com> (raw)
In-Reply-To: <20250107141015.3367194-6-rrichter@amd.com>

On Tue, 7 Jan 2025 15:09:51 +0100
Robert Richter <rrichter@amd.com> wrote:

> When adding an endpoint to a region, the root port is determined
> first. Move this directly into cxl_add_to_region(). This is in
> preparation of the initialization of endpoints that iterates the port
> hierarchy from the endpoint up to the root port.
> 
> As a side-effect the root argument is removed from the argument lists
> of cxl_add_to_region() and related functions. Now, the endpoint is the
> only parameter to add a region. This simplifies the function
> interface.
> 
> Signed-off-by: Robert Richter <rrichter@amd.com>
Seems reasonable to me.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

> ---
>  drivers/cxl/core/region.c |  6 ++++--
>  drivers/cxl/cxl.h         |  6 ++----
>  drivers/cxl/port.c        | 15 +++------------
>  3 files changed, 9 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
> index 9b3efa841c8f..752440a5c162 100644
> --- a/drivers/cxl/core/region.c
> +++ b/drivers/cxl/core/region.c
> @@ -3307,9 +3307,11 @@ static struct cxl_region *construct_region(struct cxl_root_decoder *cxlrd,
>  	return ERR_PTR(rc);
>  }
>  
> -int cxl_add_to_region(struct cxl_port *root, struct cxl_endpoint_decoder *cxled)
> +int cxl_add_to_region(struct cxl_endpoint_decoder *cxled)
>  {
>  	struct cxl_memdev *cxlmd = cxled_to_memdev(cxled);
> +	struct cxl_port *port = cxled_to_port(cxled);
> +	struct cxl_root *cxl_root __free(put_cxl_root) = find_cxl_root(port);
>  	struct range *hpa = &cxled->cxld.hpa_range;
>  	struct cxl_decoder *cxld = &cxled->cxld;
>  	struct device *cxlrd_dev, *region_dev;
> @@ -3319,7 +3321,7 @@ int cxl_add_to_region(struct cxl_port *root, struct cxl_endpoint_decoder *cxled)
>  	bool attach = false;
>  	int rc;
>  
> -	cxlrd_dev = device_find_child(&root->dev, &cxld->hpa_range,
> +	cxlrd_dev = device_find_child(&cxl_root->port.dev, &cxld->hpa_range,
>  				      match_root_decoder_by_range);
>  	if (!cxlrd_dev) {
>  		dev_err(cxlmd->dev.parent,
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index fdac3ddb8635..5c1a55181e0f 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -872,8 +872,7 @@ struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_port *port);
>  #ifdef CONFIG_CXL_REGION
>  bool is_cxl_pmem_region(struct device *dev);
>  struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev);
> -int cxl_add_to_region(struct cxl_port *root,
> -		      struct cxl_endpoint_decoder *cxled);
> +int cxl_add_to_region(struct cxl_endpoint_decoder *cxled);
>  struct cxl_dax_region *to_cxl_dax_region(struct device *dev);
>  #else
>  static inline bool is_cxl_pmem_region(struct device *dev)
> @@ -884,8 +883,7 @@ static inline struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev)
>  {
>  	return NULL;
>  }
> -static inline int cxl_add_to_region(struct cxl_port *root,
> -				    struct cxl_endpoint_decoder *cxled)
> +static inline int cxl_add_to_region(struct cxl_endpoint_decoder *cxled)
>  {
>  	return 0;
>  }
> diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
> index d2bfd1ff5492..74587a403e3d 100644
> --- a/drivers/cxl/port.c
> +++ b/drivers/cxl/port.c
> @@ -30,7 +30,7 @@ static void schedule_detach(void *cxlmd)
>  	schedule_cxl_memdev_detach(cxlmd);
>  }
>  
> -static int discover_region(struct device *dev, void *root)
> +static int discover_region(struct device *dev, void *unused)
>  {
>  	struct cxl_endpoint_decoder *cxled;
>  	int rc;
> @@ -49,7 +49,7 @@ static int discover_region(struct device *dev, void *root)
>  	 * Region enumeration is opportunistic, if this add-event fails,
>  	 * continue to the next endpoint decoder.
>  	 */
> -	rc = cxl_add_to_region(root, cxled);
> +	rc = cxl_add_to_region(cxled);
>  	if (rc)
>  		dev_dbg(dev, "failed to add to region: %#llx-%#llx\n",
>  			cxled->cxld.hpa_range.start, cxled->cxld.hpa_range.end);
> @@ -95,7 +95,6 @@ static int cxl_endpoint_port_probe(struct cxl_port *port)
>  	struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport_dev);
>  	struct cxl_dev_state *cxlds = cxlmd->cxlds;
>  	struct cxl_hdm *cxlhdm;
> -	struct cxl_port *root;
>  	int rc;
>  
>  	rc = cxl_dvsec_rr_decode(cxlds, &info);
> @@ -126,19 +125,11 @@ static int cxl_endpoint_port_probe(struct cxl_port *port)
>  	if (rc)
>  		return rc;
>  
> -	/*
> -	 * This can't fail in practice as CXL root exit unregisters all
> -	 * descendant ports and that in turn synchronizes with cxl_port_probe()
> -	 */
> -	struct cxl_root *cxl_root __free(put_cxl_root) = find_cxl_root(port);
> -
> -	root = &cxl_root->port;
> -
>  	/*
>  	 * Now that all endpoint decoders are successfully enumerated, try to
>  	 * assemble regions from committed decoders
>  	 */
> -	device_for_each_child(&port->dev, root, discover_region);
> +	device_for_each_child(&port->dev, NULL, discover_region);
>  
>  	return 0;
>  }


  parent reply	other threads:[~2025-01-13 16:52 UTC|newest]

Thread overview: 117+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-07 14:09 [PATCH v1 00/29] cxl: Add address translation support and enable AMD Zen5 platforms Robert Richter
2025-01-07 14:09 ` [PATCH v1 01/29] cxl: Remove else after return Robert Richter
2025-01-07 16:10   ` Gregory Price
2025-01-07 16:37   ` Dave Jiang
2025-01-09 12:00     ` Robert Richter
2025-01-07 14:09 ` [PATCH v1 02/29] cxl/pci: Moving code in cxl_hdm_decode_init() Robert Richter
2025-01-07 16:18   ` Gregory Price
2025-01-29 12:47     ` Robert Richter
2025-01-07 14:09 ` [PATCH v1 03/29] cxl/pci: cxl_hdm_decode_init: Move comment Robert Richter
2025-01-07 16:46   ` Gregory Price
2025-01-07 14:09 ` [PATCH v1 04/29] cxl/pci: Add comments to cxl_hdm_decode_init() Robert Richter
2025-01-07 16:51   ` Gregory Price
2025-01-13 16:47     ` Jonathan Cameron
2025-01-07 14:09 ` [PATCH v1 05/29] cxl/region: Move find_cxl_root() to cxl_add_to_region() Robert Richter
2025-01-07 16:49   ` Gregory Price
2025-01-13 16:52   ` Jonathan Cameron [this message]
2025-01-07 14:09 ` [PATCH v1 06/29] cxl/region: Factor out code to find the root decoder Robert Richter
2025-01-07 16:57   ` Gregory Price
2025-01-13 16:59   ` Jonathan Cameron
2025-01-29 13:13     ` Robert Richter
2025-01-07 14:09 ` [PATCH v1 07/29] cxl/region: Factor out code to find a root decoder's region Robert Richter
2025-01-07 16:59   ` Gregory Price
2025-01-30 16:43     ` Robert Richter
2025-01-07 14:09 ` [PATCH v1 08/29] cxl/region: Split region registration into an initialization and adding part Robert Richter
2025-01-07 18:29   ` Gregory Price
2025-01-30 16:53     ` Robert Richter
2025-01-09  1:08   ` Li Ming
2025-01-09 10:30     ` Robert Richter
2025-01-07 14:09 ` [PATCH v1 09/29] cxl/region: Use iterator to find the root port in cxl_find_root_decoder() Robert Richter
2025-01-07 17:23   ` Gregory Price
2025-01-13 18:11   ` Jonathan Cameron
2025-01-07 14:09 ` [PATCH v1 10/29] cxl/region: Add function to find a port's switch decoder by range Robert Richter
2025-01-07 18:38   ` Gregory Price
2025-01-30 16:58     ` Robert Richter
2025-01-17 21:31   ` Ben Cheatham
2025-01-30 17:02     ` Robert Richter
2025-01-07 14:09 ` [PATCH v1 11/29] cxl/region: Unfold cxl_find_root_decoder() into cxl_endpoint_initialize() Robert Richter
2025-01-07 18:41   ` Gregory Price
2025-01-07 14:09 ` [PATCH v1 12/29] cxl: Modify address translation callback for generic use Robert Richter
2025-01-07 18:44   ` Gregory Price
2025-01-31 14:19     ` Robert Richter
2025-01-17 21:31   ` Ben Cheatham
2025-01-31 14:27     ` Robert Richter
2025-01-07 14:09 ` [PATCH v1 13/29] cxl: Introduce callback to translate an HPA range from a port to its parent Robert Richter
2025-01-07 18:47   ` Gregory Price
2025-01-07 14:10 ` [PATCH v1 14/29] cxl: Introduce parent_port_of() helper Robert Richter
2025-01-07 18:50   ` Gregory Price
2025-01-13 18:20     ` Jonathan Cameron
2025-01-07 14:10 ` [PATCH v1 15/29] cxl/region: Use an endpoint's SPA range to find a region Robert Richter
2025-01-07 19:14   ` Gregory Price
2025-02-05  8:48     ` Robert Richter
2025-01-14 10:59   ` Jonathan Cameron
2025-01-31 15:46     ` Robert Richter
2025-01-17 21:31   ` Ben Cheatham
2025-02-05  9:00     ` Robert Richter
2025-01-07 14:10 ` [PATCH v1 16/29] cxl/region: Use translated HPA ranges to calculate the endpoint position Robert Richter
2025-01-07 22:01   ` Gregory Price
2025-02-05 10:38     ` Robert Richter
2025-01-17 21:31   ` Ben Cheatham
2025-02-05 10:43     ` Robert Richter
2025-01-07 14:10 ` [PATCH v1 17/29] cxl/region: Rename function to cxl_find_decoder_early() Robert Richter
2025-01-07 22:06   ` Gregory Price
2025-02-05 10:56     ` Robert Richter
2025-01-07 14:10 ` [PATCH v1 18/29] cxl/region: Avoid duplicate call of cxl_find_decoder_early() Robert Richter
2025-01-07 22:11   ` Gregory Price
2025-01-07 14:10 ` [PATCH v1 19/29] cxl/region: Use endpoint's HPA range to find the port's decoder Robert Richter
2025-01-07 22:18   ` Gregory Price
2025-02-06 10:50     ` Robert Richter
2025-01-17 21:31   ` Ben Cheatham
2025-02-06 11:03     ` Robert Richter
2025-01-07 14:10 ` [PATCH v1 20/29] cxl/region: Use translated HPA ranges " Robert Richter
2025-01-07 22:33   ` Gregory Price
2025-02-06 11:31     ` Robert Richter
2025-01-07 14:10 ` [PATCH v1 21/29] cxl/region: Lock decoders that need address translation Robert Richter
2025-01-07 22:35   ` Gregory Price
2025-02-06 13:23     ` Robert Richter
2025-01-07 14:10 ` [PATCH v1 22/29] cxl/region: Use translated HPA ranges to create a region Robert Richter
2025-01-07 23:08   ` Gregory Price
2025-02-06 13:25     ` Robert Richter
2025-01-07 14:10 ` [PATCH v1 23/29] cxl/region: Use root decoders interleaving parameters " Robert Richter
2025-01-13 17:48   ` Alison Schofield
2025-02-14 13:06     ` Robert Richter
2025-01-07 14:10 ` [PATCH v1 24/29] cxl/region: Use endpoint's SPA range to check " Robert Richter
2025-01-13 17:38   ` Alison Schofield
2025-02-14 13:09     ` Robert Richter
2025-01-07 14:10 ` [PATCH v1 25/29] cxl/amd: Enable Zen5 address translation using ACPI PRMT Robert Richter
2025-01-07 16:32   ` Robert Richter
2025-01-07 23:28   ` Gregory Price
2025-01-08 14:52     ` Robert Richter
2025-01-08 15:49       ` Gregory Price
2025-01-08 15:48   ` Gregory Price
2025-01-09 10:14     ` Robert Richter
2025-01-14 11:13       ` Jonathan Cameron
2025-01-17  7:59         ` Robert Richter
2025-01-17 11:46           ` Jonathan Cameron
2025-01-17 14:10             ` Robert Richter
2025-01-09 22:25   ` Gregory Price
2025-01-15 15:05     ` Robert Richter
2025-01-15 17:05       ` Gregory Price
2025-01-15 22:24       ` Gregory Price
2025-01-17 14:06         ` Robert Richter
2025-01-10 22:48   ` Gregory Price
2025-01-17  8:41     ` Robert Richter
2025-01-17 21:32   ` Ben Cheatham
2025-01-28  9:29     ` Robert Richter
2025-01-07 14:10 ` [PATCH v1 26/29] MAINTAINERS: CXL: Add entry for AMD platform support (CXL_AMD) Robert Richter
2025-01-07 14:10 ` [PATCH v1 27/29] cxl/region: Show message on registration failure Robert Richter
2025-01-07 23:11   ` Gregory Price
2025-01-07 14:10 ` [PATCH v1 28/29] cxl/region: Show message on broken target list Robert Richter
2025-01-07 23:12   ` Gregory Price
2025-01-14 11:16   ` Jonathan Cameron
2025-02-06 21:23     ` Robert Richter
2025-02-07 17:51       ` Jonathan Cameron
2025-02-12  9:08         ` Robert Richter
2025-01-07 14:10 ` [PATCH v1 29/29] cxl: Show message when a decoder was added to a port Robert Richter
2025-01-07 23:15   ` Gregory Price
2025-01-13 18:41 ` [PATCH v1 00/29] cxl: Add address translation support and enable AMD Zen5 platforms Alison Schofield

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