[PATCH net-next v2 1/3] net: phy: microchip_rds_ptp: Header file library changes for PEROUT

Divya Koppera
2025-01-09T10:23:19Z

This ptp header file library changes will cover PEROUT
macros that are required to generate periodic output
from pin out

Signed-off-by: Divya Koppera <divya.koppera@microchip.com>
---
v1 -> v2
- Removed redundant Macros
- Given proper naming to event and pin
---
drivers/net/phy/microchip_rds_ptp.h | 39 +++++++++++++++++++++++++++++
1 file changed, 39 insertions(+)

diff --git a/drivers/net/phy/microchip_rds_ptp.h b/drivers/net/phy/microchip_rds_ptp.h
index e95c065728b5..2a3c566b028f 100644
--- a/drivers/net/phy/microchip_rds_ptp.h
+++ b/drivers/net/phy/microchip_rds_ptp.h
@@ -130,6 +130,38 @@
#define MCHP_RDS_PTP_TSU_HARD_RESET 0xc1
#define MCHP_RDS_PTP_TSU_HARDRESET BIT(0)

+#define MCHP_RDS_PTP_CLK_TRGT_SEC_HI 0x15
+#define MCHP_RDS_PTP_CLK_TRGT_SEC_LO 0x16
+#define MCHP_RDS_PTP_CLK_TRGT_NS_HI 0x17
+#define MCHP_RDS_PTP_CLK_TRGT_NS_LO 0x18
+
+#define MCHP_RDS_PTP_CLK_TRGT_RELOAD_SEC_HI 0x19
+#define MCHP_RDS_PTP_CLK_TRGT_RELOAD_SEC_LO 0x1a
+#define MCHP_RDS_PTP_CLK_TRGT_RELOAD_NS_HI 0x1b
+#define MCHP_RDS_PTP_CLK_TRGT_RELOAD_NS_LO 0x1c
+
+#define MCHP_RDS_PTP_GEN_CFG 0x01
+#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_MASK GENMASK(11, 8)
+
+#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_SET(value) (((value) & 0xF) << 4)
+#define MCHP_RDS_PTP_GEN_CFG_RELOAD_ADD BIT(0)
+#define MCHP_RDS_PTP_GEN_CFG_POLARITY BIT(1)
+
+#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_200MS_ 13
+#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_100MS_ 12
+#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_50MS_ 11
+#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_10MS_ 10
+#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_5MS_ 9
+#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_1MS_ 8
+#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_500US_ 7
+#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_100US_ 6
+#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_50US_ 5
+#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_10US_ 4
+#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_5US_ 3
+#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_1US_ 2
+#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_500NS_ 1
+#define MCHP_RDS_PTP_GEN_CFG_LTC_EVT_100NS_ 0
+
/* Represents 1ppm adjustment in 2^32 format with
* each nsec contains 4 clock cycles in 250MHz.
* The value is calculated as following: (1/1000000)/((2^-32)/4)
@@ -138,6 +170,10 @@
#define MCHP_RDS_PTP_FIFO_SIZE 8
#define MCHP_RDS_PTP_MAX_ADJ 31249999

+#define MCHP_RDS_PTP_BUFFER_TIME 2
+#define MCHP_RDS_PTP_N_PIN 4
+#define MCHP_RDS_PTP_N_PEROUT 1
+
#define BASE_CLK(p) ((p)->clk_base_addr)
#define BASE_PORT(p) ((p)->port_base_addr)
#define PTP_MMD(p) ((p)->mmd)
@@ -176,6 +212,9 @@ struct mchp_rds_ptp_clock {
/* Lock for phc */
struct mutex ptp_lock;
u8 mmd;
+ int mchp_rds_ptp_event;
+ int event_pin;
+ struct ptp_pin_desc *pin_config;
};

struct mchp_rds_ptp_rx_ts {
--
2.17.1