From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from frasgout.his.huawei.com (frasgout.his.huawei.com [185.176.79.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D9FA0234CE3; Tue, 14 Jan 2025 11:32:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.176.79.56 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736854335; cv=none; b=cf9aC5n7NOqDayqd9yzvwDVE/Vl39a7g0pwu618BxO98qAklp4HaShb5O87fidjiASM6I2UntWIuDqViBO394Kxu/U8o8sk1d+K5IgqGkCCG5u6uR1Mc9bDyQTLCfvbiOEeluWJ0dXeUqQlLlYrVYunDcwE7D5LlYEv65MRtaJs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736854335; c=relaxed/simple; bh=7jPp419Qe6meKDsK8Bcn1TmJbIEIVl3XYa8cPrzSUnM=; h=Date:From:To:CC:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=agR4eMDLpAq0QG9KRut/bxQAmWxC/zunDxN0aYjdVbRlDkGWGc4uLMQUHCMFun3VkuvGSt1JbyOwn226MsmGawTLsV/yTQGrvV7qD1cjQ1JMCIeRTebO2NVrz8hP5KmGilzG33bXYRRIbl/EiPV8zZ85s7mosueDvcYNF+g5NBU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=185.176.79.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.18.186.216]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4YXRgB4mkCz6K9HR; Tue, 14 Jan 2025 19:27:18 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id CF6C7140A86; Tue, 14 Jan 2025 19:32:10 +0800 (CST) Received: from localhost (10.203.177.66) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 14 Jan 2025 12:32:09 +0100 Date: Tue, 14 Jan 2025 11:32:08 +0000 From: Jonathan Cameron To: Terry Bowman CC: , , , , , , , , , , , , , , , , , , , , , Shuai Xue Subject: Re: [PATCH v5 06/16] PCI/AER: Change AER driver to read UCE fatal status for all CXL PCIe Port devices Message-ID: <20250114113208.00006d08@huawei.com> In-Reply-To: <20250107143852.3692571-7-terry.bowman@amd.com> References: <20250107143852.3692571-1-terry.bowman@amd.com> <20250107143852.3692571-7-terry.bowman@amd.com> X-Mailer: Claws Mail 4.3.0 (GTK 3.24.42; x86_64-w64-mingw32) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: lhrpeml500006.china.huawei.com (7.191.161.198) To frapeml500008.china.huawei.com (7.182.85.71) On Tue, 7 Jan 2025 08:38:42 -0600 Terry Bowman wrote: > The AER service driver's aer_get_device_error_info() function doesn't read > uncorrectable (UCE) fatal error status from PCIe Upstream Port devices, > including CXL Upstream Switch Ports. As a result, fatal errors are not > logged or handled as needed for CXL PCIe Upstream Switch Port devices. > > Update the aer_get_device_error_info() function to read the UCE fatal > status for all CXL PCIe devices. Make the change such that non-CXL devices > are not affected. > > The fatal error status will be used in future patches implementing > CXL PCIe Port uncorrectable error handling and logging. > > Signed-off-by: Terry Bowman This clashes with Shuai's series adding link healthy checks. Maybe we can reuse that logic to incorporate the condition we care about here? > --- > drivers/pci/pcie/aer.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c > index 62be599e3bee..79c828bdcb6d 100644 > --- a/drivers/pci/pcie/aer.c > +++ b/drivers/pci/pcie/aer.c > @@ -1253,7 +1253,8 @@ int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info) > } else if (type == PCI_EXP_TYPE_ROOT_PORT || > type == PCI_EXP_TYPE_RC_EC || > type == PCI_EXP_TYPE_DOWNSTREAM || > - info->severity == AER_NONFATAL) { > + info->severity == AER_NONFATAL || > + (pcie_is_cxl(dev) && type == PCI_EXP_TYPE_UPSTREAM)) { > > /* Link is still healthy for IO reads */ > pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS,