From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from casper.infradead.org (casper.infradead.org [90.155.50.34]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA6F53BBE5 for ; Tue, 21 Jan 2025 09:45:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=90.155.50.34 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737452761; cv=none; b=CfZRJj9zBM3C1DIl9/V+2aB+abg/9Mhsei15WcI/UA3JYXH9iMUsi3ZQRdJ90JoOzSkf1+CkgpXXO7Pw/aRDbZzW7gkhSbyjN6SAKoOudYNDsB6GtlH43oKNR75jxuxewoDNYPVTMwN/GQBQwiB2eB63Td7hFikh6to/JzRveqg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737452761; c=relaxed/simple; bh=Q8U7zYExpyyCY7QlqVaQuSkal1XyCeWwjQ+9L53X/e8=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=n1s8Xi0eWGcbpRYI2zVKInxjAgFG9eLsFhtmXw/70WuiGLFPxYZye3/Ne4GQpc3Hr7MgJrdWn+BerVLAbpSHNSaCqbxbIYfdfAZxJvhpssKHnBbH7VaVoHjv3ojPU8JXHgmmgFd3nANNtd3g6xHnxb1n13Ggdng17eUJAqygUto= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=infradead.org; spf=none smtp.mailfrom=infradead.org; dkim=pass (2048-bit key) header.d=infradead.org header.i=@infradead.org header.b=YhClChW5; arc=none smtp.client-ip=90.155.50.34 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=infradead.org Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=infradead.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=infradead.org header.i=@infradead.org header.b="YhClChW5" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=casper.20170209; h=In-Reply-To:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description; bh=fOvAn/1eIfoUpeniWv9foq3vmq6m+tBJyxyTbXnkGDs=; b=YhClChW5FmMPeXz8n4Ca9vgZ25 zyAjQbTUqgdJHeKWEpIbyM2IUOmFjVbS1gLOufqhVlG7Pn5Ckb8ZPmUaDwlJQ6REtjGJh35MXWmkp /u7S+W1W0zqJEqO8RYydMbLijuKl+MMxd2f+1XvDzKVdN7KJd5o8aoRK046MAEK0OpVBYgKj2GNbr /noBSv5Kds3NOQB0f8BqYM4Visj9kqAYdiHe5M03XX432D7dy346286dW4m1EpqLimAkqmbmTaGQG av7mdqEYs8LCZxK7cn5Pb0sBfZXx8L2+wWkyu0ErCwD0qSh/HmXr4y9tIFI5SXSMQPqRjmy0nypUZ ryLJns8A==; Received: from 77-249-17-89.cable.dynamic.v4.ziggo.nl ([77.249.17.89] helo=noisy.programming.kicks-ass.net) by casper.infradead.org with esmtpsa (Exim 4.98 #2 (Red Hat Linux)) id 1taApK-00000005zzc-0fRd; Tue, 21 Jan 2025 09:45:42 +0000 Received: by noisy.programming.kicks-ass.net (Postfix, from userid 1000) id E33FE300619; Tue, 21 Jan 2025 10:45:40 +0100 (CET) Date: Tue, 21 Jan 2025 10:45:40 +0100 From: Peter Zijlstra To: Rik van Riel Cc: x86@kernel.org, linux-kernel@vger.kernel.org, bp@alien8.de, dave.hansen@linux.intel.com, zhengqi.arch@bytedance.com, nadav.amit@gmail.com, thomas.lendacky@amd.com, kernel-team@meta.com, linux-mm@kvack.org, akpm@linux-foundation.org, jannh@google.com, mhklinux@outlook.com, andrew.cooper3@citrix.com Subject: Re: [PATCH v6 05/12] x86/mm: add INVLPGB support code Message-ID: <20250121094540.GA5388@noisy.programming.kicks-ass.net> References: <20250120024104.1924753-1-riel@surriel.com> <20250120024104.1924753-6-riel@surriel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250120024104.1924753-6-riel@surriel.com> On Sun, Jan 19, 2025 at 09:40:13PM -0500, Rik van Riel wrote: > +/* > + * INVLPGB does broadcast TLB invalidation across all the CPUs in the system. > + * > + * The INVLPGB instruction is weakly ordered, and a batch of invalidations can > + * be done in a parallel fashion. > + * > + * TLBSYNC is used to ensure that pending INVLPGB invalidations initiated from > + * this CPU have completed. > + */ > +static inline void __invlpgb(unsigned long asid, unsigned long pcid, > + unsigned long addr, u16 extra_count, > + bool pmd_stride, unsigned long flags) > +{ > + u32 edx = (pcid << 16) | asid; > + u32 ecx = (pmd_stride << 31) | extra_count; > + u64 rax = addr | flags; > + > + /* INVLPGB; supported in binutils >= 2.36. */ > + asm volatile(".byte 0x0f, 0x01, 0xfe" : : "a" (rax), "c" (ecx), "d" (edx)); > +} So asid is always 0 (for now), but I'd feel better if that was a u16 argument, less chance funnies when someone starts using it. We should probably mask or WARN on addr having low bits set, and flags should then be a u8 or something.