From: kernel test robot <lkp@intel.com>
To: Yunhui Cui <cuiyunhui@bytedance.com>,
ajones@ventanamicro.com, alexghiti@rivosinc.com,
andybnac@gmail.com, aou@eecs.berkeley.edu, charlie@rivosinc.com,
cleger@rivosinc.com, conor.dooley@microchip.com,
conor@kernel.org, corbet@lwn.net, evan@rivosinc.com,
jesse@rivosinc.com, linux-doc@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org,
linux-riscv@lists.infradead.org, palmer@dabbelt.com,
paul.walmsley@sifive.com, samuel.holland@sifive.com,
shuah@kernel.org
Cc: oe-kbuild-all@lists.linux.dev
Subject: Re: [PATCH v5 2/3] RISC-V: hwprobe: Expose Zicbom extension and its block size
Date: Tue, 21 Jan 2025 23:05:42 +0800 [thread overview]
Message-ID: <202501212220.5GHTtuF7-lkp@intel.com> (raw)
In-Reply-To: <20250115024024.84365-3-cuiyunhui@bytedance.com>
Hi Yunhui,
kernel test robot noticed the following build warnings:
[auto build test WARNING on shuah-kselftest/next]
[also build test WARNING on shuah-kselftest/fixes linus/master v6.13 next-20250121]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Yunhui-Cui/RISC-V-Enable-cbo-clean-flush-in-usermode/20250115-104456
base: https://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest.git next
patch link: https://lore.kernel.org/r/20250115024024.84365-3-cuiyunhui%40bytedance.com
patch subject: [PATCH v5 2/3] RISC-V: hwprobe: Expose Zicbom extension and its block size
config: riscv-randconfig-r133-20250121 (https://download.01.org/0day-ci/archive/20250121/202501212220.5GHTtuF7-lkp@intel.com/config)
compiler: clang version 20.0.0git (https://github.com/llvm/llvm-project c23f2417dc5f6dc371afb07af5627ec2a9d373a0)
reproduce: (https://download.01.org/0day-ci/archive/20250121/202501212220.5GHTtuF7-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202501212220.5GHTtuF7-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> arch/riscv/kernel/sys_hwprobe.c:284:30: warning: implicit conversion from 'unsigned long long' to 'unsigned long' changes value from 1125899906842624 to 0 [-Wconstant-conversion]
284 | if (hwprobe_ext0_has(cpus, RISCV_HWPROBE_EXT_ZICBOM))
| ~~~~~~~~~~~~~~~~ ^~~~~~~~~~~~~~~~~~~~~~~~
arch/riscv/include/uapi/asm/hwprobe.h:76:41: note: expanded from macro 'RISCV_HWPROBE_EXT_ZICBOM'
76 | #define RISCV_HWPROBE_EXT_ZICBOM (1ULL << 50)
| ~~~~~^~~~~
1 warning generated.
vim +284 arch/riscv/kernel/sys_hwprobe.c
244
245 static void hwprobe_one_pair(struct riscv_hwprobe *pair,
246 const struct cpumask *cpus)
247 {
248 switch (pair->key) {
249 case RISCV_HWPROBE_KEY_MVENDORID:
250 case RISCV_HWPROBE_KEY_MARCHID:
251 case RISCV_HWPROBE_KEY_MIMPID:
252 hwprobe_arch_id(pair, cpus);
253 break;
254 /*
255 * The kernel already assumes that the base single-letter ISA
256 * extensions are supported on all harts, and only supports the
257 * IMA base, so just cheat a bit here and tell that to
258 * userspace.
259 */
260 case RISCV_HWPROBE_KEY_BASE_BEHAVIOR:
261 pair->value = RISCV_HWPROBE_BASE_BEHAVIOR_IMA;
262 break;
263
264 case RISCV_HWPROBE_KEY_IMA_EXT_0:
265 hwprobe_isa_ext0(pair, cpus);
266 break;
267
268 case RISCV_HWPROBE_KEY_CPUPERF_0:
269 case RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF:
270 pair->value = hwprobe_misaligned(cpus);
271 break;
272
273 case RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF:
274 pair->value = hwprobe_vec_misaligned(cpus);
275 break;
276
277 case RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE:
278 pair->value = 0;
279 if (hwprobe_ext0_has(cpus, RISCV_HWPROBE_EXT_ZICBOZ))
280 pair->value = riscv_cboz_block_size;
281 break;
282 case RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE:
283 pair->value = 0;
> 284 if (hwprobe_ext0_has(cpus, RISCV_HWPROBE_EXT_ZICBOM))
285 pair->value = riscv_cbom_block_size;
286 break;
287 case RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS:
288 pair->value = user_max_virt_addr();
289 break;
290
291 case RISCV_HWPROBE_KEY_TIME_CSR_FREQ:
292 pair->value = riscv_timebase;
293 break;
294
295 /*
296 * For forward compatibility, unknown keys don't fail the whole
297 * call, but get their element key set to -1 and value set to 0
298 * indicating they're unrecognized.
299 */
300 default:
301 pair->key = -1;
302 pair->value = 0;
303 break;
304 }
305 }
306
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
next prev parent reply other threads:[~2025-01-21 15:06 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-15 2:40 [PATCH v5 0/3] Enable Zicbom in usermode Yunhui Cui
2025-01-15 2:40 ` [PATCH v5 1/3] RISC-V: Enable cbo.clean/flush " Yunhui Cui
2025-01-15 2:40 ` [PATCH v5 2/3] RISC-V: hwprobe: Expose Zicbom extension and its block size Yunhui Cui
2025-01-15 9:17 ` Andrew Jones
2025-01-16 4:58 ` Samuel Holland
2025-01-21 15:05 ` kernel test robot [this message]
2025-01-21 15:29 ` Andrew Jones
2025-01-24 3:26 ` [External] " yunhui cui
2025-01-15 2:40 ` [PATCH v5 3/3] RISC-V: selftests: Add TEST_ZICBOM into CBO tests Yunhui Cui
2025-02-25 13:21 ` [PATCH v5 0/3] Enable Zicbom in usermode Alexandre Ghiti
2025-02-25 13:27 ` [External] " yunhui cui
2025-02-25 14:07 ` Alexandre Ghiti
2025-02-26 11:10 ` yunhui cui
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