From: Maxime Chevallier <maxime.chevallier@bootlin.com>
To: Andrew Lunn <andrew@lunn.ch>
Cc: Ninad Palsule <ninad@linux.ibm.com>,
Jacky Chou <jacky_chou@aspeedtech.com>,
"andrew+netdev@lunn.ch" <andrew+netdev@lunn.ch>,
"andrew@codeconstruct.com.au" <andrew@codeconstruct.com.au>,
"conor+dt@kernel.org" <conor+dt@kernel.org>,
"davem@davemloft.net" <davem@davemloft.net>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"eajames@linux.ibm.com" <eajames@linux.ibm.com>,
"edumazet@google.com" <edumazet@google.com>,
"joel@jms.id.au" <joel@jms.id.au>,
"krzk+dt@kernel.org" <krzk+dt@kernel.org>,
"kuba@kernel.org" <kuba@kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-aspeed@lists.ozlabs.org" <linux-aspeed@lists.ozlabs.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"minyard@acm.org" <minyard@acm.org>,
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"openipmi-developer@lists.sourceforge.net"
<openipmi-developer@lists.sourceforge.net>,
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"ratbert@faraday-tech.com" <ratbert@faraday-tech.com>,
"robh@kernel.org" <robh@kernel.org>
Subject: Re: 回覆: 回覆: [PATCH v2 05/10] ARM: dts: aspeed: system1: Add RGMII support
Date: Wed, 22 Jan 2025 15:05:42 +0100 [thread overview]
Message-ID: <20250122150542.55d483e6@fedora.home> (raw)
In-Reply-To: <c83f0193-ce24-4a3e-87d1-f52587e13ca4@lunn.ch>
> > Can we consider an update in the kernel doc along these lines :
> >
> > ---
> > Documentation/networking/phy.rst | 19 +++++++++++--------
> > 1 file changed, 11 insertions(+), 8 deletions(-)
> >
> > diff --git a/Documentation/networking/phy.rst b/Documentation/networking/phy.rst
> > index f64641417c54..7ab77f9867a0 100644
> > --- a/Documentation/networking/phy.rst
> > +++ b/Documentation/networking/phy.rst
> > @@ -106,14 +106,17 @@ Whenever possible, use the PHY side RGMII delay for these reasons:
> > configure correctly a specified delay enables more designs with similar delay
> > requirements to be operated correctly
> >
> > -For cases where the PHY is not capable of providing this delay, but the
> > -Ethernet MAC driver is capable of doing so, the correct phy_interface_t value
> > -should be PHY_INTERFACE_MODE_RGMII, and the Ethernet MAC driver should be
> > -configured correctly in order to provide the required transmit and/or receive
> > -side delay from the perspective of the PHY device. Conversely, if the Ethernet
> > -MAC driver looks at the phy_interface_t value, for any other mode but
> > -PHY_INTERFACE_MODE_RGMII, it should make sure that the MAC-level delays are
> > -disabled.
> > +The MAC driver may add delays if the PCB doesn't include any. This can be
> > +detected based on firmware "rx-internal-delay-ps" and "tx-internal-delay-ps"
> > +properties.
> > +
> > +When the MAC driver can insert the delays, it should always do so when these
> > +properties are present and non-zero, regardless of the RGMII mode specified.
> > +
> > +However, the MAC driver must adjust the PHY_INTERFACE_MODE_RGMII_* mode it passes
> > +to the connected PHY device (through phy_attach or phylink_create() for example)
> > +to account for MAC-side delay insertion, so that the the PHY device knows
> > +if any delays still needs insertion on either TX or RX paths.
>
> You dropped:
>
> For cases where the PHY is not capable of providing this delay...
>
> This is something i would like to keep, to strengthen that we really
> do want the PHY to add the delays. Many MACs are capable of adding
> delays, but we don't want them to, the PHY should do it, so we have
> consistency.
>
> The language i've tried to use is that "rx-internal-delay-ps" and
> "tx-internal-delay-ps" can be used to fine tune the delays, so i'm
> expecting their values to be small, because the PHY is adding the 2ns,
> and the MAC is just adding/removing 0-200ps etc. I've also used the
> same terminology for PHY drivers, the PHY DT properties for delays are
> used for fine tuning, but the basic 2ns on/off comes from the phy-mode
> passed to phylib.
>
> If it is just fine tuning, and not adding the full 2ns, it should just
> pass phy-mode straight through.
>
> So your text becomes something like:
>
> The MAC driver may fine tune the delays. This can be configured
> based on firmware "rx-internal-delay-ps" and "tx-internal-delay-ps"
> properties. These values are expected to be small, not the full 2ns
> delay.
>
> A MAC driver inserting these fine tuning delays should always do so
> when these properties are present and non-zero, regardless of the
> RGMII mode specified.
>
> Then we can address when the MAC adds the full 2ns.
>
> For cases where the PHY is not capable of providing the 2ns delay,
> the MAC must provide it, if the phy-mode indicates the PCB is not
> providing the delays. The MAC driver must adjust the
> PHY_INTERFACE_MODE_RGMII_* mode it passes to the connected PHY
> device (through phy_attach or phylink_create() for example) to
> account for MAC-side delay insertion, so that the the PHY device
> does not add additional delays.
>
> I also think we need something near the beginning like:
>
> The device tree property phy-mode describes the hardware. When used
> with RGMII, its value indicates if the hardware, i.e. the PCB,
> provides the 2ns delay required for RGMII. A phy-mode of 'rgmii'
> indicates the PCB is adding the 2ns delay. For other values, the
> MAC/PHY pair must insert the needed 2ns delay, with the strong
> preference the PHY adds the delay.
Thanks Andrew for the suggestions, your wording is definitely better
than mine :) I'll queue that for when net-next re-opens.
Maxime
next prev parent reply other threads:[~2025-01-22 14:05 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-08 3:54 [PATCH v2 05/10] ARM: dts: aspeed: system1: Add RGMII support Jacky Chou
2025-01-08 17:52 ` Andrew Lunn
2025-01-08 19:14 ` Ninad Palsule
2025-01-08 20:17 ` Andrew Lunn
2025-01-08 22:31 ` Ninad Palsule
2025-01-08 23:08 ` Andrew Lunn
2025-01-09 10:33 ` 回覆: " Jacky Chou
2025-01-09 13:21 ` Andrew Lunn
2025-01-09 14:25 ` Ninad Palsule
2025-01-09 14:54 ` Andrew Lunn
2025-01-10 9:15 ` 回覆: " Jacky Chou
2025-01-10 14:04 ` Andrew Lunn
2025-01-10 14:54 ` Ninad Palsule
2025-01-10 15:38 ` Andrew Lunn
2025-01-22 13:07 ` Maxime Chevallier
2025-01-22 13:39 ` Andrew Lunn
2025-01-22 14:05 ` Maxime Chevallier [this message]
2025-01-13 6:18 ` 回覆: " Jacky Chou
2025-01-10 14:05 ` Ninad Palsule
2025-01-13 6:22 ` 回覆: " Jacky Chou
2025-01-13 14:26 ` Ninad Palsule
2025-01-13 14:38 ` Andrew Lunn
2025-01-15 2:57 ` 回覆: " Jacky Chou
2025-01-15 3:05 ` Andrew Lunn
2025-01-15 4:22 ` 回覆: " Jacky Chou
2025-01-15 13:30 ` Andrew Lunn
2025-01-20 6:59 ` 回覆: " Jacky Chou
2025-01-09 14:32 ` Ninad Palsule
2025-01-09 14:48 ` Andrew Lunn
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