[PATCH 0/2] RISC-V IOMMU HPM support

Zong Li
2025-01-15T03:03:19Z

This serie implements the RISC-V IOMMU hardware performance monitor
includes both counting and sampling modes.

The specification does not define an event ID for counting the number of
clock cycles, meaning there is no associated `iohpmevt0`. However, we
need an event for counting cycle, so we reserve the maximum event ID for
it.

The interrupt handler needs to be a primary handler instead of a
threaded function because 'pt_regs` is empty when threading the IRQ.
However `pt_regs` is required by perf_event_overflow()

Changed in RFC:
- Rebase onto v6.13-rc7
- Clear interrupt pending before handling interrupt
- Fix the counter value issue caused by OF bit in the cycle counter.
- Invoke riscv_iommu_hpm_disable() instead of riscv_iommu_pmu_uninit()
in riscv_iommu_remove()

Zong Li (2):
iommu/riscv: add RISC-V IOMMU PMU support
iommu/riscv: support HPM and interrupt handling

drivers/iommu/riscv/Makefile | 2 +-
drivers/iommu/riscv/iommu-bits.h | 16 +
drivers/iommu/riscv/iommu-pmu.c | 486 +++++++++++++++++++++++++++++++
drivers/iommu/riscv/iommu.c | 65 +++++
drivers/iommu/riscv/iommu.h | 8 +
5 files changed, 576 insertions(+), 1 deletion(-)
create mode 100644 drivers/iommu/riscv/iommu-pmu.c

--
2.17.1