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smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=jbwi+ctq; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="jbwi+ctq" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1D1F9C4CED3; Thu, 23 Jan 2025 21:29:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1737667780; bh=FEs7jQ869xS1Q7igMZTQDDuVl1J0onigxN6VNDB8Jow=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=jbwi+ctq44Dg0Y4cj9ZrNxVPLEKbRBScbEi43bABcv+nEooXfABtGgi4RotLU7Ch4 7YcHD9nzVmDEHWpGsTep7UtFer7VG2v3CfA6Qog3eO2QB1NPeNS1AiP8FA5A/qwEWx Z4a98jwlH+6YdolG2+CzqQXsCJg/MS3Lq33GFywyQ63T5PCZLCJSAKobhF8LQm0D9V BWbxNTcsqybGgWFiTBMPes+8CEgOIda9NtlKXZpxW33Kto1Lp3rx695qyTNfHGPyhf 69HOkH5PTmphh1tQoqVXmaFuwBzTP4LKV7+fDkmqULV0lQdjbkd1EblLAc3iplK1D2 GRATt+p71dLog== Date: Thu, 23 Jan 2025 15:29:38 -0600 From: Rob Herring To: Chen Wang Cc: u.kleine-koenig@baylibre.com, aou@eecs.berkeley.edu, arnd@arndb.de, unicorn_wang@outlook.com, conor+dt@kernel.org, guoren@kernel.org, inochiama@outlook.com, krzk+dt@kernel.org, palmer@dabbelt.com, paul.walmsley@sifive.com, tglx@linutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, chao.wei@sophgo.com, xiaoguang.xing@sophgo.com, fengchun.li@sophgo.com, samuel.holland@sifive.com, christophe.jaillet@wanadoo.fr Subject: Re: [PATCH v3 1/3] dt-bindings: interrupt-controller: Add Sophgo SG2042 MSI Message-ID: <20250123212938.GA390972-robh@kernel.org> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Wed, Jan 15, 2025 at 02:33:23PM +0800, Chen Wang wrote: > From: Chen Wang > > Add binding for Sophgo SG2042 MSI controller. > > Signed-off-by: Chen Wang > --- > .../sophgo,sg2042-msi.yaml | 58 +++++++++++++++++++ > 1 file changed, 58 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-msi.yaml > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-msi.yaml b/Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-msi.yaml > new file mode 100644 > index 000000000000..f641df191787 > --- /dev/null > +++ b/Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-msi.yaml > @@ -0,0 +1,58 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/interrupt-controller/sophgo,sg2042-msi.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Sophgo SG2042 MSI Controller > + > +maintainers: > + - Chen Wang > + > +description: > + This interrupt controller is in Sophgo SG2042 for transforming interrupts from > + PCIe MSI to PLIC interrupts. > + > +allOf: > + - $ref: /schemas/interrupts.yaml# Drop this. > + - $ref: /schemas/interrupt-controller/msi-controller.yaml# > + > +properties: > + compatible: > + const: sophgo,sg2042-msi > + > + reg: > + items: > + - description: msi doorbell address > + - description: clear register > + > + reg-names: > + items: > + - const: doorbell > + - const: clr > + > + msi-controller: true > + > + msi-ranges: > + maxItems: 1 You need #msi-cells. > + > +required: > + - compatible > + - reg > + - reg-names > + - msi-controller > + - msi-ranges > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include > + msi-controller@30000000 { > + compatible = "sophgo,sg2042-msi"; > + reg = <0x30000000 0x4>, <0x30000008 0x4>; > + reg-names = "doorbell", "clr"; > + msi-controller; > + msi-ranges = <&plic 64 IRQ_TYPE_LEVEL_HIGH 32>; > + interrupt-parent = <&plic>; > + }; > -- > 2.34.1 >