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From: Conor Dooley <conor@kernel.org>
To: E Shattow <e@freeshell.de>
Cc: Emil Renner Berthing <kernel@esmil.dk>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	devicetree@vger.kernel.org
Subject: Re: [RFC PATCH v1 1/3] riscv: dts: starfive: jh7110: add timer node
Date: Fri, 24 Jan 2025 16:40:40 +0000	[thread overview]
Message-ID: <20250124-unweave-stainable-debbb0e75cd4@spud> (raw)
In-Reply-To: <b62cfcc1-5d10-43a1-80ae-f09a53c739de@freeshell.de>

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On Fri, Jan 24, 2025 at 03:19:33AM -0800, E Shattow wrote:
> 
> On 1/13/25 10:39, Conor Dooley wrote:
> > On Thu, Jan 02, 2025 at 12:41:21PM -0800, E Shattow wrote:
> > > no idea if this does anything useful; not needed for boot
> > > 
> > > Signed-off-by: E Shattow <e@freeshell.de>
> > > ---
> > >   arch/riscv/boot/dts/starfive/jh7110.dtsi | 9 +++++++++
> > >   1 file changed, 9 insertions(+)
> > > 
> > > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > > index 0d8339357bad..0bc922b3ae8a 100644
> > > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > > @@ -344,6 +344,15 @@ tdm_ext: tdm-ext-clock {
> > >   		#clock-cells = <0>;
> > >   	};
> > > +	timer {
> > > +		compatible = "riscv, timer";
> > 
> > compatible has an extra space, so won't do anything!
> > 
> > > +		interrupts-extended = <&cpu0_intc 5>,
> > > +				      <&cpu1_intc 5>,
> > > +				      <&cpu2_intc 5>,
> > > +				      <&cpu3_intc 5>,
> > > +				      <&cpu4_intc 5>;
> > > +	};
> > > +
> > >   	soc {
> > >   		compatible = "simple-bus";
> > >   		interrupt-parent = <&plic>;
> > > -- 
> > > 2.45.2
> > > 
> 
> That extra space is my error and does not exist in U-Boot. Good catch! So,
> when corrected it appears to boot either way with or without and not any
> change in functionality that I can discern. My priority then for this series
> is to drop this patch as something unnecessary.

I don't mind having it, if it makes the hw description more complete,
even if not used.

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  reply	other threads:[~2025-01-24 16:40 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-02 20:41 [RFC PATCH v1 0/3] riscv: dts: starfive: jh7110: More U-Boot downstream changes for JH7110 E Shattow
2025-01-02 20:41 ` [RFC PATCH v1 1/3] riscv: dts: starfive: jh7110: add timer node E Shattow
2025-01-13 18:39   ` Conor Dooley
2025-01-24 11:19     ` E Shattow
2025-01-24 16:40       ` Conor Dooley [this message]
2025-01-02 20:41 ` [RFC PATCH v1 2/3] riscv: dts: starfive: jh7110: add DRAM memory controller node E Shattow
2025-01-13 18:41   ` Conor Dooley
2025-01-02 20:41 ` [RFC PATCH v1 3/3] riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader E Shattow
2025-01-13 18:41 ` [RFC PATCH v1 0/3] riscv: dts: starfive: jh7110: More U-Boot downstream changes for JH7110 Conor Dooley

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