Re: [PATCH v3 4/4] PCI: qcom: Enable ECAM feature

Krishna Chaitanya Chundru
2025-01-24T08:21:36Z

On 1/24/2025 12:28 PM, Manivannan Sadhasivam wrote:
> On Tue, Jan 21, 2025 at 02:32:22PM +0530, Krishna Chaitanya Chundru wrote:
>> The ELBI registers falls after the DBI space, PARF_SLV_DBI_ELBI register
>> gives us the offset from which ELBI starts. so use this offset and cfg
>> win to map these regions instead of doing the ioremap again.
>>
>> On root bus, we have only the root port. Any access other than that
>> should not go out of the link and should return all F's. Since the iATU
>> is configured for the buses which starts after root bus, block the
>> transactions starting from function 1 of the root bus to the end of
>> the root bus (i.e from dbi_base + 4kb to dbi_base + 1MB) from going
>> outside the link through ECAM blocker through PARF registers.
>>
>> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
>> ---
>> drivers/pci/controller/dwc/pcie-qcom.c | 81 ++++++++++++++++++++++++++++++++--
>> 1 file changed, 77 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
>> index dc102d8bd58c..cf94718d3059 100644
>> --- a/drivers/pci/controller/dwc/pcie-qcom.c
>> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
>> @@ -52,6 +52,7 @@
>> #define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8
>> #define PARF_Q2A_FLUSH 0x1ac
>> #define PARF_LTSSM 0x1b0
>> +#define PARF_SLV_DBI_ELBI 0x1b4
>> #define PARF_INT_ALL_STATUS 0x224
>> #define PARF_INT_ALL_CLEAR 0x228
>> #define PARF_INT_ALL_MASK 0x22c
>> @@ -61,6 +62,17 @@
>> #define PARF_DBI_BASE_ADDR_V2_HI 0x354
>> #define PARF_SLV_ADDR_SPACE_SIZE_V2 0x358
>> #define PARF_SLV_ADDR_SPACE_SIZE_V2_HI 0x35c
>> +#define PARF_BLOCK_SLV_AXI_WR_BASE 0x360
>> +#define PARF_BLOCK_SLV_AXI_WR_BASE_HI 0x364
>> +#define PARF_BLOCK_SLV_AXI_WR_LIMIT 0x368
>> +#define PARF_BLOCK_SLV_AXI_WR_LIMIT_HI 0x36c
>> +#define PARF_BLOCK_SLV_AXI_RD_BASE 0x370
>> +#define PARF_BLOCK_SLV_AXI_RD_BASE_HI 0x374
>> +#define PARF_BLOCK_SLV_AXI_RD_LIMIT 0x378
>> +#define PARF_BLOCK_SLV_AXI_RD_LIMIT_HI 0x37c
>> +#define PARF_ECAM_BASE 0x380
>> +#define PARF_ECAM_BASE_HI 0x384
>> +
>> #define PARF_NO_SNOOP_OVERIDE 0x3d4
>> #define PARF_ATU_BASE_ADDR 0x634
>> #define PARF_ATU_BASE_ADDR_HI 0x638
>> @@ -84,6 +96,7 @@
>>
>> /* PARF_SYS_CTRL register fields */
>> #define MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN BIT(29)
>> +#define PCIE_ECAM_BLOCKER_EN BIT(26)
>> #define MST_WAKEUP_EN BIT(13)
>> #define SLV_WAKEUP_EN BIT(12)
>> #define MSTR_ACLK_CGC_DIS BIT(10)
>> @@ -294,15 +307,60 @@ static void qcom_ep_reset_deassert(struct qcom_pcie *pcie)
>> usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
>> }
>>
>> +static int qcom_pci_config_ecam(struct dw_pcie_rp *pp)
>> +{
>
> void qcom_pci_config_ecam()?
>
>> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>> + struct qcom_pcie *pcie = to_qcom_pcie(pci);
>> + u64 addr, addr_end;
>> + u32 val;
>> +
>> + /* Set the ECAM base */
>> + writel(lower_32_bits(pci->dbi_phys_addr), pcie->parf + PARF_ECAM_BASE);
>
> You can use _relaxed variants in this function.
>
>> + writel(upper_32_bits(pci->dbi_phys_addr), pcie->parf + PARF_ECAM_BASE_HI);
>> +
>> + /*
>> + * The only device on root bus is the Root Port. Any access other than that
>> + * should not go out of the link and should return all F's. Since the iATU
>> + * is configured for the buses which starts after root bus, block the transactions
>> + * starting from function 1 of the root bus to the end of the root bus (i.e from
>> + * dbi_base + 4kb to dbi_base + 1MB) from going outside the link.
>
> Why can't you impose this limitation with the iATU mapping itself? I mean, why
> can't the mapping be limited to 4K to cover only device 00.0? I believe the min
> iATU window size is 4K on all platforms.
>
There is no iATU mapping for pcie0 the first 4k i,e 00.0.0 is local
memory( i.e dbi memory). we configure iATU when we want to specific the
transctions to go with this type, message etc. The entire 1 MB for bus 0
in not configured through iATU. Any read/write to the PCIe memory region
will goto outside the PCIe link, if there is iATU mapped for that memory
the the transction goes out with iATU injected type or message etc.

we can't use iATU for this case where we do want the transctions going
out side the link.
>> + */
>> + addr = pci->dbi_phys_addr + SZ_4K;
>> + writel(lower_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_WR_BASE);
>> + writel(upper_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_WR_BASE_HI);
>> +
>> + writel(lower_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_RD_BASE);
>> + writel(upper_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_RD_BASE_HI);
>> +
>> + addr_end = pci->dbi_phys_addr + SZ_1M - 1;
>> +
>> + writel(lower_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_WR_LIMIT);
>> + writel(upper_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_WR_LIMIT_HI);
>> +
>> + writel(lower_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_RD_LIMIT);
>> + writel(upper_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_RD_LIMIT_HI);
>> +
>> + val = readl(pcie->parf + PARF_SYS_CTRL);
>> + val |= PCIE_ECAM_BLOCKER_EN;
>> + writel(val, pcie->parf + PARF_SYS_CTRL);
>
> nit; newline
>
>> + return 0;
>> +}
>> +
>> static int qcom_pcie_start_link(struct dw_pcie *pci)
>> {
>> struct qcom_pcie *pcie = to_qcom_pcie(pci);
>> + int ret;
>>
>> if (pcie_link_speed[pci->max_link_speed] == PCIE_SPEED_16_0GT) {
>> qcom_pcie_common_set_16gt_equalization(pci);
>> qcom_pcie_common_set_16gt_lane_margining(pci);
>> }
>>
>> + if (pci->pp.ecam_mode) {
>> + ret = qcom_pci_config_ecam(&pci->pp);
>> + if (ret)
>> + return ret;
>> + }
>> /* Enable Link Training state machine */
>> if (pcie->cfg->ops->ltssm_enable)
>> pcie->cfg->ops->ltssm_enable(pcie);
>> @@ -1233,6 +1291,7 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp)
>> {
>> struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>> struct qcom_pcie *pcie = to_qcom_pcie(pci);
>> + u16 offset;
>> int ret;
>>
>> qcom_ep_reset_assert(pcie);
>> @@ -1241,6 +1300,11 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp)
>> if (ret)
>> return ret;
>>
>> + if (pp->ecam_mode) {
>> + offset = readl(pcie->parf + PARF_SLV_DBI_ELBI);
>> + pcie->elbi = pci->dbi_base + offset;
>
> Can't you derive this offset for non-ECAM mode also?
>
we can derive it for ecam mode we are not doing any devm_ioremap as it
will part of dbi space only. For non ecam mode we need to do ioremap to
the dbi physical address + offset to elbi size. As the elbi size can
vary it is best to use this way only.
>> + }
>> +
>> ret = phy_set_mode_ext(pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC);
>> if (ret)
>> goto err_deinit;
>> @@ -1613,6 +1677,13 @@ static int qcom_pcie_probe(struct platform_device *pdev)
>> pci->ops = &dw_pcie_ops;
>> pp = &pci->pp;
>>
>> + pp->bridge = devm_pci_alloc_host_bridge(dev, 0);
>> + if (!pp->bridge) {
>> + ret = -ENOMEM;
>> + goto err_pm_runtime_put;
>> + }
>> +
>> + pci->pp.ecam_mode = dw_pcie_ecam_supported(pp);
>
> you should be able to set this in designware-host.c
>
we need this to skip elbi ioremap or not in below before we can
dw_pcie_host_init().
>> pcie->pci = pci;
>>
>> pcie->cfg = pcie_cfg;
>> @@ -1629,10 +1700,12 @@ static int qcom_pcie_probe(struct platform_device *pdev)
>> goto err_pm_runtime_put;
>> }
>>
>> - pcie->elbi = devm_platform_ioremap_resource_byname(pdev, "elbi");
>> - if (IS_ERR(pcie->elbi)) {
>> - ret = PTR_ERR(pcie->elbi);
>> - goto err_pm_runtime_put;
>> + if (!pp->ecam_mode) {
>> + pcie->elbi = devm_platform_ioremap_resource_byname(pdev, "elbi");
>> + if (IS_ERR(pcie->elbi)) {
>> + ret = PTR_ERR(pcie->elbi);
>> + goto err_pm_runtime_put;
>
> You can drop this if the ELBI offset can be derived from PARF register on all
> platforms.
>
As mentioned above, we can derive the offset but in non drv mode we need
to have ioremap. Better stay this way.

- Krishna Chaitanya.
> - Mani
>