From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B1D2158DC6 for ; Fri, 24 Jan 2025 18:34:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.11 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737743661; cv=none; b=qPk7bXfFflwDq4HAB4WNiq/WBunp6jacsfmK2KaD4mTB75l3YmE54m0m9bkjfuSwRwcu8R+6+p1B8ta/5Um/xenOTFVPPHrh4mho7Jg9ZdDqLG5ChZHD4GaXeN+vGMnAg9zLVyCFDLe+k0j0nUAoTAC30pzauZHz7wEke8Laczg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737743661; c=relaxed/simple; bh=2bC2LU9le5yu5edk3nttL4p6YIHO2udf+0kqWJcKVyw=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version; b=FYHLIS7ZP75IslUKFU1UGEhPtUkmkUcfIKX1DUhofgaTxHgJCiVhq2CFuyH93JIQUZg6frfv72jgyo88AHLSjcBIWPUnwtUO4Dbkmddkm+SJWwLNMgPmuRAoelpoEx3ZH6bpP8JWfnlwTLpV0wkTVnPpaStV6y/vUIsPcH+ZMJo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=W7HuUhKL; arc=none smtp.client-ip=192.198.163.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="W7HuUhKL" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1737743659; x=1769279659; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=2bC2LU9le5yu5edk3nttL4p6YIHO2udf+0kqWJcKVyw=; b=W7HuUhKLERpMT3Cg1B0tlIhpxQ0XIZ2JSsEtY5uwxFRcqSuHs0vumU16 VNnNsw0XToIeOfZyYENLTkna7J4rdLYkBm/mdWT37JFd9JHtPdLHFXgmQ /ABjxZknoY0d6yDQ434xgi1fDjEemIblRviApyk4QlTjqi320kmaBRS8o F7xzRkqiUcntZnuo0YRHb74Q4NWcQDgXR8heSfBM8nLRTrcvfDrn1kjaW JZYz6f4SxhNRGKaV6SKtOBxVfCCS5s9+8Q7+VSgxZUQDZMMVTCJSjkQOC VYmnqN+lN7yNm1+Aqj+fEPnQk4iMNKFEFaDqk2DC+QAAyBXG8N1EeB/dH A==; X-CSE-ConnectionGUID: rQhJBDleRZWZ4mQFQaV+Sw== X-CSE-MsgGUID: 6Lh155IfQ16nDWHPhT11tw== X-IronPort-AV: E=McAfee;i="6700,10204,11325"; a="48872707" X-IronPort-AV: E=Sophos;i="6.13,231,1732608000"; d="scan'208";a="48872707" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jan 2025 10:34:18 -0800 X-CSE-ConnectionGUID: UvJNDakjQ+2/5YDYbW75cQ== X-CSE-MsgGUID: NqiWpR2/QRiC58l4sNv02A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,231,1732608000"; d="scan'208";a="107643398" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by fmviesa006.fm.intel.com with ESMTP; 24 Jan 2025 10:34:18 -0800 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, namhyung@kernel.org, irogers@google.com, adrian.hunter@intel.com, alexander.shishkin@linux.intel.com, linux-kernel@vger.kernel.org Cc: Kan Liang Subject: [PATCH] perf/x86/intel: Clean up PEBS-via-PT on hybrid Date: Fri, 24 Jan 2025 10:34:32 -0800 Message-Id: <20250124183432.3565061-1-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.38.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Kan Liang The PEBS-via-PT feature is exposed for the e-core of some hybrid platforms, e.g., ADL and MTL. But it never works. $ dmesg | grep PEBS [ 1.793888] core: cpu_atom PMU driver: PEBS-via-PT $ perf record -c 1000 -e '{intel_pt/branch=0/, cpu_atom/cpu-cycles,aux-output/pp}' -C8 Error: The sys_perf_event_open() syscall returned with 22 (Invalid argument) for event (cpu_atom/cpu-cycles,aux-output/pp). "dmesg | grep -i perf" may provide additional information. The "PEBS-via-PT" is printed if the corresponding bit of per-PMU capabilities is set. Since the feature is supported by the e-core HW, perf sets the bit for e-core. However, for Intel PT, if a feature is not supported on all CPUs, it is not supported at all. The PEBS-via-PT event cannot be created successfully. The PEBS-via-PT is no longer enumerated on the latest hybrid platform. It will be deprecated on future platforms with Arch PEBS. Let's remove it from the existing hybrid platforms. Fixes: d9977c43bff8 ("perf/x86: Register hybrid PMUs") Signed-off-by: Kan Liang Cc: Adrian Hunter Cc: Alexander Shishkin --- arch/x86/events/intel/core.c | 10 ---------- arch/x86/events/intel/ds.c | 2 +- 2 files changed, 1 insertion(+), 11 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 7f1b6b90a5fb..0a1030eb6db8 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -4981,11 +4981,6 @@ static void intel_pmu_check_hybrid_pmus(struct x86_hybrid_pmu *pmu) else pmu->intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS); - if (pmu->intel_cap.pebs_output_pt_available) - pmu->pmu.capabilities |= PERF_PMU_CAP_AUX_OUTPUT; - else - pmu->pmu.capabilities &= ~PERF_PMU_CAP_AUX_OUTPUT; - intel_pmu_check_event_constraints(pmu->event_constraints, pmu->cntr_mask64, pmu->fixed_cntr_mask64, @@ -5063,9 +5058,6 @@ static bool init_hybrid_pmu(int cpu) pr_info("%s PMU driver: ", pmu->name); - if (pmu->intel_cap.pebs_output_pt_available) - pr_cont("PEBS-via-PT "); - pr_cont("\n"); x86_pmu_show_pmu_cap(&pmu->pmu); @@ -6420,11 +6412,9 @@ static __always_inline int intel_pmu_init_hybrid(enum hybrid_pmu_type pmus) pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities; if (pmu->pmu_type & hybrid_small_tiny) { pmu->intel_cap.perf_metrics = 0; - pmu->intel_cap.pebs_output_pt_available = 1; pmu->mid_ack = true; } else if (pmu->pmu_type & hybrid_big) { pmu->intel_cap.perf_metrics = 1; - pmu->intel_cap.pebs_output_pt_available = 0; pmu->late_ack = true; } } diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index 13a78a8a2780..123b0e4392b4 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -2742,7 +2742,7 @@ void __init intel_ds_init(void) } pr_cont("PEBS fmt%d%c%s, ", format, pebs_type, pebs_qual); - if (!is_hybrid() && x86_pmu.intel_cap.pebs_output_pt_available) { + if (x86_pmu.intel_cap.pebs_output_pt_available) { pr_cont("PEBS-via-PT, "); x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_AUX_OUTPUT; } -- 2.38.1