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From: Peter Zijlstra <peterz@infradead.org>
To: "Liang, Kan" <kan.liang@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>,
	Dapeng Mi <dapeng1.mi@linux.intel.com>,
	Ingo Molnar <mingo@redhat.com>,
	Arnaldo Carvalho de Melo <acme@kernel.org>,
	Namhyung Kim <namhyung@kernel.org>,
	Ian Rogers <irogers@google.com>,
	Adrian Hunter <adrian.hunter@intel.com>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Eranian Stephane <eranian@google.com>,
	linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
	Dapeng Mi <dapeng1.mi@intel.com>
Subject: Re: [PATCH 03/20] perf/x86/intel: Parse CPUID archPerfmonExt leaves for non-hybrid CPUs
Date: Mon, 27 Jan 2025 17:44:06 +0100	[thread overview]
Message-ID: <20250127164406.GN16742@noisy.programming.kicks-ass.net> (raw)
In-Reply-To: <85588439-ec0e-4824-8193-f0737880ecb9@linux.intel.com>

On Mon, Jan 27, 2025 at 10:19:34AM -0500, Liang, Kan wrote:
> 
> 
> On 2025-01-23 1:58 p.m., Andi Kleen wrote:
> >> +	/*
> >> +	 * The archPerfmonExt (0x23) includes an enhanced enumeration of
> >> +	 * PMU architectural features with a per-core view. For non-hybrid,
> >> +	 * each core has the same PMU capabilities. It's good enough to
> >> +	 * update the x86_pmu from the booting CPU. For hybrid, the x86_pmu
> >> +	 * is used to keep the common capabilities. Still keep the values
> >> +	 * from the leaf 0xa. The core specific update will be done later
> >> +	 * when a new type is online.
> >> +	 */
> >> +	if (!is_hybrid() && boot_cpu_has(X86_FEATURE_ARCH_PERFMON_EXT))
> >> +		update_pmu_cap(NULL);
> > 
> > It seems ugly to have these different code paths. Couldn't non hybrid
> > use x86_pmu in the same way? I assume it would be a larger patch.
> 
> The current non-hybrid is initialized in the intel_pmu_init(). But some
> of the initialization code for the hybrid is in the
> intel_pmu_cpu_starting(). Yes, it's better to move it together. It
> should be a larger patch. Since it's impacted other features, a separate
> patch set should be required.

IIRC the problem was that there were SKUs with the same FMS that were
both hybrid and non-hybrid and we wouldn't know until we brought up the
CPUs.

Thomas rewrote the topology bits since, so maybe we can do beter these
days.


  reply	other threads:[~2025-01-27 16:44 UTC|newest]

Thread overview: 47+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-23 14:07 [PATCH 00/20] Arch-PEBS and PMU supports for Clearwater Forest Dapeng Mi
2025-01-23 14:07 ` [PATCH 01/20] perf/x86/intel: Add PMU support " Dapeng Mi
2025-01-27 16:26   ` Peter Zijlstra
2025-02-06  1:31     ` Mi, Dapeng
2025-02-06  7:53       ` Peter Zijlstra
2025-02-06  9:35         ` Mi, Dapeng
2025-02-06  9:39           ` Peter Zijlstra
2025-01-23 14:07 ` [PATCH 02/20] perf/x86/intel: Fix ARCH_PERFMON_NUM_COUNTER_LEAF Dapeng Mi
2025-01-27 16:29   ` Peter Zijlstra
2025-01-27 16:43     ` Liang, Kan
2025-01-27 21:29       ` Peter Zijlstra
2025-01-28  0:28         ` Liang, Kan
2025-01-23 14:07 ` [PATCH 03/20] perf/x86/intel: Parse CPUID archPerfmonExt leaves for non-hybrid CPUs Dapeng Mi
2025-01-23 18:58   ` Andi Kleen
2025-01-27 15:19     ` Liang, Kan
2025-01-27 16:44       ` Peter Zijlstra [this message]
2025-02-06  2:09         ` Mi, Dapeng
2025-01-23 14:07 ` [PATCH 04/20] perf/x86/intel: Decouple BTS initialization from PEBS initialization Dapeng Mi
2025-01-23 14:07 ` [PATCH 05/20] perf/x86/intel: Rename x86_pmu.pebs to x86_pmu.ds_pebs Dapeng Mi
2025-01-23 14:07 ` [PATCH 06/20] perf/x86/intel: Initialize architectural PEBS Dapeng Mi
2025-01-28 11:22   ` Peter Zijlstra
2025-02-06  2:25     ` Mi, Dapeng
2025-01-23 14:07 ` [PATCH 07/20] perf/x86/intel/ds: Factor out common PEBS processing code to functions Dapeng Mi
2025-01-23 14:07 ` [PATCH 08/20] perf/x86/intel: Process arch-PEBS records or record fragments Dapeng Mi
2025-01-23 14:07 ` [PATCH 09/20] perf/x86/intel: Factor out common functions to process PEBS groups Dapeng Mi
2025-01-23 14:07 ` [PATCH 10/20] perf/x86/intel: Allocate arch-PEBS buffer and initialize PEBS_BASE MSR Dapeng Mi
2025-01-23 14:07 ` [PATCH 11/20] perf/x86/intel: Setup PEBS constraints base on counter & pdist map Dapeng Mi
2025-01-27 16:07   ` Liang, Kan
2025-02-06  2:47     ` Mi, Dapeng
2025-02-06 15:01       ` Liang, Kan
2025-02-07  1:27         ` Mi, Dapeng
2025-01-23 14:07 ` [PATCH 12/20] perf/x86/intel: Setup PEBS data configuration and enable legacy groups Dapeng Mi
2025-01-23 14:07 ` [PATCH 13/20] perf/x86/intel: Add SSP register support for arch-PEBS Dapeng Mi
2025-01-24  5:16   ` Andi Kleen
2025-01-27 15:38     ` Liang, Kan
2025-01-23 14:07 ` [PATCH 14/20] perf/x86/intel: Add counter group " Dapeng Mi
2025-01-23 14:07 ` [PATCH 15/20] perf/core: Support to capture higher width vector registers Dapeng Mi
2025-01-23 14:07 ` [PATCH 16/20] perf/x86/intel: Support arch-PEBS vector registers group capturing Dapeng Mi
2025-01-23 14:07 ` [PATCH 17/20] perf tools: Support to show SSP register Dapeng Mi
2025-01-23 16:15   ` Ian Rogers
2025-02-06  2:57     ` Mi, Dapeng
2025-01-23 14:07 ` [PATCH 18/20] perf tools: Support to capture more vector registers (common part) Dapeng Mi
2025-01-23 16:42   ` Ian Rogers
2025-01-27 15:50     ` Liang, Kan
2025-02-06  3:12       ` Mi, Dapeng
2025-01-23 14:07 ` [PATCH 19/20] perf tools: Support to capture more vector registers (x86/Intel part) Dapeng Mi
2025-01-23 14:07 ` [PATCH 20/20] perf tools/tests: Add vector registers PEBS sampling test Dapeng Mi

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