From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE57B1DF744 for ; Wed, 29 Jan 2025 16:20:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738167603; cv=none; b=fFtlfLnbbmIET8OxghzzQGcOmiHMeVWPhyJyAgyGIKBwIFUBVegIcQh7v8jFgp834bn6DzZ4Gg5SMRy6jPl25tfcEwZ59bBAKojS/ffiWeFdZT6mx19RxsG5rvb9y+NKGWdUFE6YBfnRdNmW1vyl78blEOmdLetC4pYqM2IuWMk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738167603; c=relaxed/simple; bh=/xr+O0nuPR2GbK+yqEfII6MLsaJ1DD5+2fiy11H5sCc=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=hlyBIrJwfX+yq3c1G94oyJHD3TSHIYEH3XqfYcoj0c4844sS1nFj6fmR7DgSlTVd35SlbDqZvaXvtaxz2pt98hr91/f0wjQNMcneCXWjS+0TAh/qBCWCWwb97237sNsMWPBA9JXU9Tpe+BU3IpXrEDCP7nZOJyVf2rCxSlmX5TI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Urw3YPkZ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Urw3YPkZ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0D4B0C4CED1; Wed, 29 Jan 2025 16:20:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738167602; bh=/xr+O0nuPR2GbK+yqEfII6MLsaJ1DD5+2fiy11H5sCc=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=Urw3YPkZjPPT5WidYxkLObM+dPfv7nk/ZDwg8dYZ2EK6zofbejxnCq7ojL7TY+/6w PqJzOgXpNy66YGhsy5oRPiURW3XJRkkBZCzp0HwzfJDdyGLVRptk6edRYsxBPazN5t u6+MDG1WwbrD6nqRehRLcnWOcHUBpjgtzPEo3w9oRUnRLhdlyWQdF5rCMKldFK1tnB IXE+oZy5J3eWqIApDeGCWcRO47iQfOO3Aa1fP9xv2qa8rxL3zVLULWD6cssheO9i4t QfSVIjuesoLvBpQQTaichU3DLt3UZlbokEsDqB4rybpeZRfE72jQ3VTrIPPOKOEVDB j2AGdmpFHc4xQ== Date: Wed, 29 Jan 2025 16:19:58 +0000 From: Conor Dooley To: Aleksandar Rikalo Cc: linux-riscv@lists.infradead.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Andrew Jones , Christoph =?iso-8859-1?Q?M=FCllner?= , linux-kernel@vger.kernel.org, Djordje Todorovic Subject: Re: [PATCH v3] riscv: Fix the PAUSE Opcode for MIPS P8700. Message-ID: <20250129-museum-slider-3bb634d124de@spud> References: <20250129131703.733098-1-arikalo@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="eMHOSPIWF9cimNJf" Content-Disposition: inline In-Reply-To: <20250129131703.733098-1-arikalo@gmail.com> --eMHOSPIWF9cimNJf Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Jan 29, 2025 at 02:17:03PM +0100, Aleksandar Rikalo wrote: > From: Djordje Todorovic >=20 > The riscv MIPS P8700 uses a different opcode for PAUSE. > It is a =E2=80=98hint=E2=80=99 encoding of the SLLI instruction, with rd= =3D0, rs1=3D0 and > imm=3D5. It will behave as a NOP instruction if no additional behavior > beyond that of SLLI is implemented. You say p8700, but the erratum will be applied on all systems that are identified as using a mips cpu. Why's that? > +void mips_errata_patch_func(struct alt_entry *begin, > + struct alt_entry *end, > + unsigned long archid, > + unsigned long impid, > + unsigned int stage) > +{ > + struct alt_entry *alt; > + > + BUILD_BUG_ON(ERRATA_MIPS_NUMBER >=3D RISCV_VENDOR_EXT_ALTERNATIVES_BASE= ); > + > + if (stage =3D=3D RISCV_ALTERNATIVES_EARLY_BOOT) > + return; > + > + for (alt =3D begin; alt < end; alt++) { > + if (alt->vendor_id !=3D MIPS_VENDOR_ID) > + continue; > + > + if (alt->patch_id >=3D ERRATA_MIPS_NUMBER) { > + WARN(1, "MIPS errata id:%d not in kernel errata list\n", > + alt->patch_id); > + continue; > + } > + > + mutex_lock(&text_mutex); > + patch_text_nosync(ALT_OLD_PTR(alt), ALT_ALT_PTR(alt), alt->alt_len); > + mutex_unlock(&text_mutex); > + } > +} > diff --git a/tools/arch/riscv/include/asm/vdso/processor.h b/tools/arch/r= iscv/include/asm/vdso/processor.h > index 662aca039848..880f26a24f69 100644 > --- a/tools/arch/riscv/include/asm/vdso/processor.h > +++ b/tools/arch/riscv/include/asm/vdso/processor.h > @@ -14,7 +14,10 @@ static inline void cpu_relax(void) > __asm__ __volatile__ ("div %0, %0, zero" : "=3Dr" (dummy)); > #endif > =20 > -#ifdef CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE > +#ifdef CONFIG_ERRATA_MIPS_P8700_PAUSE_OPCODE > + /* MIPS P8700 pause opcode */ > + __asm__ __volatile__ (".4byte 0x00501013"); > +#elif CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE > /* > * Reduce instruction retirement. > * This assumes the PC changes. What about when the erratum is enabled and the toolchain supports Zihintpause? Why don't you use the same implementation as the !tools copy of the header? (I'm not sure why they're different in the first place). --eMHOSPIWF9cimNJf Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZ5pVLgAKCRB4tDGHoIJi 0jzsAPwPO2TbzV0CLmLLBBF2VSrcHtpUJGHN1svBVFjInp45sgEAu9U57bs56soB 2YnL7XfSl9TVJ6uqSY1eBiGZuTmexgE= =kZev -----END PGP SIGNATURE----- --eMHOSPIWF9cimNJf--