From: Dheeraj Kumar Srivastava <dheerajkumar.srivastava@amd.com>
To: <joro@8bytes.org>, <suravee.suthikulpanit@amd.com>,
<will@kernel.org>, <robin.murphy@arm.com>,
<linux-kernel@vger.kernel.org>, <iommu@lists.linux.dev>
Cc: <vasant.hegde@amd.com>
Subject: [PATCH v3 7/8] iommu/amd: Add debugfs support to dump IRT Table
Date: Thu, 6 Feb 2025 11:30:02 +0530 [thread overview]
Message-ID: <20250206060003.685-8-dheerajkumar.srivastava@amd.com> (raw)
In-Reply-To: <20250206060003.685-1-dheerajkumar.srivastava@amd.com>
In cases where we have an issue in the device interrupt path with IOMMU
interrupt remapping enabled, dumping valid IRT table entries for the device
is very useful and good input for debugging the issue.
eg.
To dump irte entries for a particular device
#echo "c4:00.0" > /sys/kernel/debug/iommu/amd/devid
#cat /sys/kernel/debug/iommu/amd/irqtbl | less
or
#echo "0000:c4:00.0" > /sys/kernel/debug/iommu/amd/devid
#cat /sys/kernel/debug/iommu/amd/irqtbl | less
Signed-off-by: Dheeraj Kumar Srivastava <dheerajkumar.srivastava@amd.com>
---
drivers/iommu/amd/debugfs.c | 89 +++++++++++++++++++++++++++++++++++++
1 file changed, 89 insertions(+)
diff --git a/drivers/iommu/amd/debugfs.c b/drivers/iommu/amd/debugfs.c
index 1377795814d1..0aff1d616108 100644
--- a/drivers/iommu/amd/debugfs.c
+++ b/drivers/iommu/amd/debugfs.c
@@ -11,6 +11,7 @@
#include <linux/pci.h>
#include "amd_iommu.h"
+#include "../irq_remapping.h"
static struct dentry *amd_iommu_debugfs;
@@ -250,6 +251,92 @@ static int iommu_devtbl_show(struct seq_file *m, void *unused)
}
DEFINE_SHOW_ATTRIBUTE(iommu_devtbl);
+static void dump_128_irte(struct seq_file *m, struct irq_remap_table *table)
+{
+ struct irte_ga *ptr, *irte;
+ int index;
+
+ for (index = 0; index < MAX_IRQS_PER_TABLE; index++) {
+ ptr = (struct irte_ga *)table->table;
+ irte = &ptr[index];
+
+ if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
+ !irte->lo.fields_vapic.valid)
+ continue;
+ else if (!irte->lo.fields_remap.valid)
+ continue;
+ seq_printf(m, "IRT[%04d] %016llx%016llx\n", index, irte->hi.val, irte->lo.val);
+ }
+}
+
+static void dump_32_irte(struct seq_file *m, struct irq_remap_table *table)
+{
+ union irte *ptr, *irte;
+ int index;
+
+ for (index = 0; index < MAX_IRQS_PER_TABLE; index++) {
+ ptr = (union irte *)table->table;
+ irte = &ptr[index];
+
+ if (!irte->fields.valid)
+ continue;
+ seq_printf(m, "IRT[%04d] %08x\n", index, irte->val);
+ }
+}
+
+static void dump_irte(struct seq_file *m, u16 devid, struct amd_iommu_pci_seg *pci_seg)
+{
+ struct irq_remap_table *table;
+ unsigned long flags;
+
+ table = pci_seg->irq_lookup_table[devid];
+ if (!table) {
+ seq_printf(m, "IRQ lookup table not set for %04x:%02x:%02x:%x\n",
+ pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid));
+ return;
+ }
+
+ seq_printf(m, "DeviceId %04x:%02x:%02x:%x\n", pci_seg->id, PCI_BUS_NUM(devid),
+ PCI_SLOT(devid), PCI_FUNC(devid));
+
+ raw_spin_lock_irqsave(&table->lock, flags);
+ if (AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
+ dump_128_irte(m, table);
+ else
+ dump_32_irte(m, table);
+ seq_puts(m, "\n");
+ raw_spin_unlock_irqrestore(&table->lock, flags);
+}
+
+static int iommu_irqtbl_show(struct seq_file *m, void *unused)
+{
+ struct amd_iommu_pci_seg *pci_seg;
+ u16 devid, seg;
+
+ if (!irq_remapping_enabled) {
+ seq_puts(m, "Interrupt remapping is disabled\n");
+ return 0;
+ }
+
+ if (sbdf < 0) {
+ seq_puts(m, "Please provide valid device id input\n");
+ return 0;
+ }
+
+ seg = PCI_SBDF_TO_SEGID(sbdf);
+ devid = PCI_SBDF_TO_DEVID(sbdf);
+
+ for_each_pci_segment(pci_seg) {
+ if (pci_seg->id != seg)
+ continue;
+ dump_irte(m, devid, pci_seg);
+ break;
+ }
+
+ return 0;
+}
+DEFINE_SHOW_ATTRIBUTE(iommu_irqtbl);
+
void amd_iommu_debugfs_setup(void)
{
struct amd_iommu *iommu;
@@ -272,4 +359,6 @@ void amd_iommu_debugfs_setup(void)
&devid_fops);
debugfs_create_file("devtbl", 0444, amd_iommu_debugfs, NULL,
&iommu_devtbl_fops);
+ debugfs_create_file("irqtbl", 0444, amd_iommu_debugfs, NULL,
+ &iommu_irqtbl_fops);
}
--
2.25.1
next prev parent reply other threads:[~2025-02-06 6:02 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-06 5:59 [PATCH v3 0/8] Introduce debugfs support in IOMMU Dheeraj Kumar Srivastava
2025-02-06 5:59 ` [PATCH v3 1/8] iommu/amd: Refactor AMD IOMMU debugfs initial setup Dheeraj Kumar Srivastava
2025-03-13 10:27 ` Vasant Hegde
2025-02-06 5:59 ` [PATCH v3 2/8] iommu/amd: Add debugfs support to dump IOMMU MMIO registers Dheeraj Kumar Srivastava
2025-03-13 10:28 ` Vasant Hegde
2025-03-17 11:22 ` Dheeraj Kumar Srivastava
2025-02-06 5:59 ` [PATCH v3 3/8] iommu/amd: Add debugfs support to dump IOMMU Capability registers Dheeraj Kumar Srivastava
2025-03-13 10:32 ` Vasant Hegde
2025-03-17 11:23 ` Dheeraj Kumar Srivastava
2025-02-06 5:59 ` [PATCH v3 4/8] iommu/amd: Add debugfs support to dump IOMMU command buffer Dheeraj Kumar Srivastava
2025-03-13 10:38 ` Vasant Hegde
2025-03-17 11:24 ` Dheeraj Kumar Srivastava
2025-02-06 6:00 ` [PATCH v3 5/8] iommu/amd: Add support for device id user input Dheeraj Kumar Srivastava
2025-03-13 10:52 ` Vasant Hegde
2025-03-17 11:25 ` Dheeraj Kumar Srivastava
2025-02-06 6:00 ` [PATCH v3 6/8] iommu/amd: Add debugfs support to dump device table Dheeraj Kumar Srivastava
2025-02-06 6:00 ` Dheeraj Kumar Srivastava [this message]
2025-03-13 11:03 ` [PATCH v3 7/8] iommu/amd: Add debugfs support to dump IRT Table Vasant Hegde
2025-03-17 11:26 ` Dheeraj Kumar Srivastava
2025-02-06 6:00 ` [PATCH v3 8/8] iommu/amd: Add documentation for AMD IOMMU debugfs support Dheeraj Kumar Srivastava
2025-02-06 8:56 ` [PATCH v3 0/8] Introduce debugfs support in IOMMU Suthikulpanit, Suravee
2025-03-07 8:17 ` Dheeraj Kumar Srivastava
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