Re: [PATCH 0/9] riscv: Unaligned access speed probing fixes and skipping

[Andrew Jones <ajones@ventanamicro.com>]

On Mon, Feb 10, 2025 at 03:28:13PM +0530, Anup Patel wrote:
> On Mon, Feb 10, 2025 at 2:56 PM Andrew Jones <ajones@ventanamicro.com> wrote:
> >
> > On Sat, Feb 08, 2025 at 01:29:42PM +0530, Anup Patel wrote:
> > > On Fri, Feb 7, 2025 at 9:49 PM Andrew Jones <ajones@ventanamicro.com> wrote:
> > > >
> > > > The first six patches of this series are fixes and cleanups of the
> > > > unaligned access speed probing code. The next two patches introduce
> > > > support to skip probing by matching vendor/arch/imp ids and checking a
> > > > table for the access speed type. The last patch applies the new skip
> > > > support to Ventana harts.
> > >
> > > Alternatively, we can also skip probing misaligned access when Zicclsm
> > > extension is present in the ISA string. The Zicclsm extension is defined
> > > as part of the ratified RVA23 profile.
> >
> > The definition of Zicclsm doesn't explicitly state that misaligned word
> > accesses will be faster than byte accesses to the same addresses. There's
> > also this spec issue[1] which appears to state that Zicclsm cannot be used
> > to infer fast misaligned accesses.
> >
> > But, like Charlie suggests, maybe we should advocate the creation of an
> > extension (or "named feature") which allows specifically advertising that
> > misaligned accesses are fast.
> >
> > [1] https://github.com/riscv/riscv-isa-manual/issues/1611
> 
> I am not sure when such an extension would show up so for now
> skipping unaligned tests based on implementation ID seems
> reasonable.
> 
> Also, it seems this series is totally skipping the existing boot-time
> print for fast unaligned access. Please try to keep the boot-time
> print in some form.

Sure. We have hwprobe, but now that people are likely used to seeing it
in dmesg, then we should probably keep something there.

Thanks,
drew