Re: [PATCH 0/9] riscv: Unaligned access speed probing fixes and skipping

[Andrew Jones <ajones@ventanamicro.com>]

On Sat, Feb 08, 2025 at 01:29:42PM +0530, Anup Patel wrote:
> On Fri, Feb 7, 2025 at 9:49 PM Andrew Jones <ajones@ventanamicro.com> wrote:
> >
> > The first six patches of this series are fixes and cleanups of the
> > unaligned access speed probing code. The next two patches introduce
> > support to skip probing by matching vendor/arch/imp ids and checking a
> > table for the access speed type. The last patch applies the new skip
> > support to Ventana harts.
> 
> Alternatively, we can also skip probing misaligned access when Zicclsm
> extension is present in the ISA string. The Zicclsm extension is defined
> as part of the ratified RVA23 profile.

The definition of Zicclsm doesn't explicitly state that misaligned word
accesses will be faster than byte accesses to the same addresses. There's
also this spec issue[1] which appears to state that Zicclsm cannot be used
to infer fast misaligned accesses.

But, like Charlie suggests, maybe we should advocate the creation of an
extension (or "named feature") which allows specifically advertising that
misaligned accesses are fast.

[1] https://github.com/riscv/riscv-isa-manual/issues/1611

Thanks,
drew

> 
> Regards,
> Anup
> 
> >
> > (I'd be happy to split the fixes from the new skip support if we want to
> > discuss the skip support independently, but I want to base on the fixes
> > and I'm not sure if patchwork supports Based-on: $MESSAGE_ID/$LORE_URL
> > or not at the moment, so I'm just posting together for now in order to
> > be able to check for my patchwork green lights!)
> >
> > Thanks,
> > drew
> >
> > Andrew Jones (9):
> >   riscv: Annotate unaligned access init functions
> >   riscv: Fix riscv_online_cpu_vec
> >   riscv: Fix check_unaligned_access_all_cpus
> >   riscv: Change check_unaligned_access_speed_all_cpus to void
> >   riscv: Fix set up of cpu hotplug callbacks
> >   riscv: Fix set up of vector cpu hotplug callback
> >   riscv: Prepare for unaligned access type table lookups
> >   riscv: Implement check_unaligned_access_table
> >   riscv: Add Ventana unaligned access table entries
> >
> >  arch/riscv/include/asm/cpufeature.h        |   4 +-
> >  arch/riscv/include/asm/vendorid_list.h     |   1 +
> >  arch/riscv/kernel/traps_misaligned.c       |  14 +-
> >  arch/riscv/kernel/unaligned_access_speed.c | 278 ++++++++++++++-------
> >  4 files changed, 200 insertions(+), 97 deletions(-)
> >
> > --
> > 2.48.1
> >