From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BCCB4250BE8; Mon, 10 Feb 2025 22:15:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739225750; cv=none; b=mcZ8jtDfih1nVLwIDP7E4qGYDWiXGhaSn1v80eVtfTZn+myfN7BncmQ0nfP3CZ388VNq5Kqv+5HFItkOv+CVGcJ4OmQ1pyxEZM5+fafa9zKbG1TxMn2k+wkSJ8fm5tTd/UG5tPSV07xs9W9MZAkD3XNfjRXIkGrAprGqIvbNfKk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739225750; c=relaxed/simple; bh=Ta9r01ygHu0VhF+GktkmCTovIWBE4YWLVxYhbtVA1IU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=sAPWUVTENiqawrJqUI/UtFKlVoc5aNt6TQyMA3CR+1MPyMuy1oiEWoSAWSv1QPHKrIPRYSTQ4hH3jEHuPhMf29gpOCG/3nCFoAkoqRHA4erQoUmI0SHPhErL5nHhce33YhsQnSXi56IVYXPcqbTGgus9d9qVYeLB6ID+LcsrhaQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=Ygen3BBU; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="Ygen3BBU" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 51AMFVCJ206216 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 10 Feb 2025 16:15:31 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1739225731; bh=lPm9IUD69eZu1j7NgjSqFSM4EnJWFUoj35jLv4pCV1E=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Ygen3BBUwaYiuiFJybBOY+DZrXf495ms0BWFtuIdUxUW9e1BDH+dB+li+EYp55Da9 YTcPAgzTODiVlhJ9eqMIKgqr/Rn7Rtn/jLHAh0k9vg5d+axQv1H6g54JeUac5ivozK 3ayNjD09rjuNEv9znHa7BE0rzyjV8dzQAg2U9yKg= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 51AMFV9o016606 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 10 Feb 2025 16:15:31 -0600 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 10 Feb 2025 16:15:30 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 10 Feb 2025 16:15:30 -0600 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 51AMFUZ8112628; Mon, 10 Feb 2025 16:15:30 -0600 From: Judith Mendez To: Nishanth Menon , Vignesh Raghavendra CC: Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Andrew Davis , Hari Nagalla , Judith Mendez Subject: [PATCH v5 06/10] arm64: dts: ti: k3-am62p5-sk: Enable IPC with remote processors Date: Mon, 10 Feb 2025 16:15:26 -0600 Message-ID: <20250210221530.1234009-7-jm@ti.com> X-Mailer: git-send-email 2.48.0 In-Reply-To: <20250210221530.1234009-1-jm@ti.com> References: <20250210221530.1234009-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea From: Devarsh Thakkar For each remote proc, reserve memory for IPC and bind the mailbox assignments. Two memory regions are reserved for each remote processor. The first region of 1MB of memory is used for Vring shared buffers and the second region is used as external memory to the remote processor for the resource table and for tracebuffer allocations. Signed-off-by: Devarsh Thakkar Signed-off-by: Hari Nagalla Signed-off-by: Judith Mendez --- Changes since v4: - Drop SRAM node for am62px MCU R5fSS0 core0 --- arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 50 ++++++++++++++++++++++--- 1 file changed, 44 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts index ad71d2f27f538..9609727d042d3 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -48,6 +48,30 @@ reserved-memory { #size-cells = <2>; ranges; + mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@9b800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9b800000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@9b900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9b900000 0x00 0xf00000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9c800000 0x00 0x100000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-memory@9c900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9c900000 0x00 0x1e00000>; + no-map; + }; + secure_tfa_ddr: tfa@9e780000 { reg = <0x00 0x9e780000 0x00 0x80000>; no-map; @@ -57,12 +81,6 @@ secure_ddr: optee@9e800000 { reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ no-map; }; - - wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9c900000 0x00 0x01e00000>; - no-map; - }; }; vmain_pd: regulator-0 { @@ -638,6 +656,26 @@ mbox_mcu_r5_0: mbox-mcu-r5-0 { }; }; +&wkup_r5fss0 { + status = "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes = <&mailbox0_cluster0 &mbox_r5_0>; + memory-region = <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0 { + status = "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + &main_uart0 { pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; -- 2.48.0