Re: [PATCH v7 08/17] cxl/pci: Map CXL PCIe Upstream Switch Port RAS registers

Bowman, Terry
2025-02-14T19:50:45Z

On 2/14/2025 9:15 AM, Jonathan Cameron wrote:
> On Tue, 11 Feb 2025 13:24:35 -0600
> Terry Bowman <terry.bowman@amd.com> wrote:
>
>> Add logic to map CXL PCIe Upstream Switch Port (USP) RAS registers.
>>
>> Introduce 'struct cxl_regs' member into 'struct cxl_port' to cache a
>> pointer to the CXL Upstream Port's mapped RAS registers.
>>
>> Also, introduce cxl_uport_init_ras_reporting() to perform the USP RAS
>> register mapping. This is similar to the existing
>> cxl_dport_init_ras_reporting() but for USP devices.
>>
>> The USP may have multiple downstream endpoints. Before mapping RAS
>> registers check if the registers are already mapped.
>>
>> Introduce a mutex for synchronizing accesses to the cached RAS
>> mapping.
>>
>> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
>> Reviewed-by: Gregory Price <gourry@gourry.net>
>> /**
>> * cxl_dport_init_ras_reporting - Setup CXL RAS report on this dport
>> * @dport: the cxl_dport that needs to be initialized
>> @@ -801,7 +819,6 @@ void cxl_dport_init_ras_reporting(struct cxl_dport *dport)
>> BIT(CXL_CM_CAP_CAP_ID_RAS)))
>> dev_err(dport_dev, "Failed to map RAS capability\n");
>> mutex_unlock(&ras_init_mutex);
>> -
> Grumpy hat (it is Friday afternoon). Shouldn't be in this patch!
Thanks. This is removed from this patch in next revision.

Terry