Re: [PATCH v7 13/17] cxl/pci: Add trace logging for CXL PCIe Port RAS errors

Dave Jiang
2025-02-12T00:19:09Z

On 2/11/25 5:17 PM, Dave Jiang wrote:
>
>
> On 2/11/25 12:24 PM, Terry Bowman wrote:
>> The CXL drivers use kernel trace functions for logging Endpoint and
>> Restricted CXL host (RCH) Downstream Port RAS errors. Similar functionality
>> is required for CXL Root Ports, CXL Downstream Switch Ports, and CXL
>> Upstream Switch Ports.
>>
>> Introduce trace logging functions for both RAS correctable and
>> uncorrectable errors specific to CXL PCIe Ports. Additionally, update
>> the CXL Port Protocol Error handlers to invoke these new trace functions.
>>
>> Examples of the output from these changes is below.
>>
>> Correctable error:
>> cxl_port_aer_correctable_error: device=port1 parent=root0 status='Received Error From Physical Layer'
>
> Is there any way to identify if the error comes from the USP or DSP? Specifically the PCI devname for the specific port?

Hah I spoke too soon. You addressed it in the next patch. :)

DJ

>>
>> Uncorrectable error:
>> cxl_port_aer_uncorrectable_error: device=port1 parent=root0 status: 'Memory Byte Enable Parity Error' first_error: 'Memory Byte Enable Parity Erro'
>>
>> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
>> Reviewed-by: Alejandro Lucero <alucerop@amd.com>
>> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>
> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
>
>> ---
>> drivers/cxl/core/pci.c | 4 ++++
>> drivers/cxl/core/trace.h | 47 ++++++++++++++++++++++++++++++++++++++++
>> 2 files changed, 51 insertions(+)
>>
>> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
>> index 3f13d9dfb610..9a3090dae46a 100644
>> --- a/drivers/cxl/core/pci.c
>> +++ b/drivers/cxl/core/pci.c
>> @@ -671,6 +671,8 @@ static void __cxl_handle_cor_ras(struct device *dev,
>>
>> if (is_cxl_memdev(dev))
>> trace_cxl_aer_correctable_error(to_cxl_memdev(dev), status);
>> + else if (is_cxl_port(dev))
>> + trace_cxl_port_aer_correctable_error(dev, status);
>> }
>>
>> static void cxl_handle_endpoint_cor_ras(struct cxl_dev_state *cxlds)
>> @@ -730,6 +732,8 @@ static pci_ers_result_t __cxl_handle_ras(struct device *dev, void __iomem *ras_b
>> header_log_copy(ras_base, hl);
>> if (is_cxl_memdev(dev))
>> trace_cxl_aer_uncorrectable_error(to_cxl_memdev(dev), status, fe, hl);
>> + else if (is_cxl_port(dev))
>> + trace_cxl_port_aer_uncorrectable_error(dev, status, fe, hl);
>>
>> writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr);
>>
>> diff --git a/drivers/cxl/core/trace.h b/drivers/cxl/core/trace.h
>> index cea706b683b5..b536233ac210 100644
>> --- a/drivers/cxl/core/trace.h
>> +++ b/drivers/cxl/core/trace.h
>> @@ -48,6 +48,34 @@
>> { CXL_RAS_UC_IDE_RX_ERR, "IDE Rx Error" } \
>> )
>>
>> +TRACE_EVENT(cxl_port_aer_uncorrectable_error,
>> + TP_PROTO(struct device *dev, u32 status, u32 fe, u32 *hl),
>> + TP_ARGS(dev, status, fe, hl),
>> + TP_STRUCT__entry(
>> + __string(devname, dev_name(dev))
>> + __string(parent, dev_name(dev->parent))
>> + __field(u32, status)
>> + __field(u32, first_error)
>> + __array(u32, header_log, CXL_HEADERLOG_SIZE_U32)
>> + ),
>> + TP_fast_assign(
>> + __assign_str(devname);
>> + __assign_str(parent);
>> + __entry->status = status;
>> + __entry->first_error = fe;
>> + /*
>> + * Embed the 512B headerlog data for user app retrieval and
>> + * parsing, but no need to print this in the trace buffer.
>> + */
>> + memcpy(__entry->header_log, hl, CXL_HEADERLOG_SIZE);
>> + ),
>> + TP_printk("device=%s parent=%s status: '%s' first_error: '%s'",
>> + __get_str(devname), __get_str(parent),
>> + show_uc_errs(__entry->status),
>> + show_uc_errs(__entry->first_error)
>> + )
>> +);
>> +
>> TRACE_EVENT(cxl_aer_uncorrectable_error,
>> TP_PROTO(const struct cxl_memdev *cxlmd, u32 status, u32 fe, u32 *hl),
>> TP_ARGS(cxlmd, status, fe, hl),
>> @@ -96,6 +124,25 @@ TRACE_EVENT(cxl_aer_uncorrectable_error,
>> { CXL_RAS_CE_PHYS_LAYER_ERR, "Received Error From Physical Layer" } \
>> )
>>
>> +TRACE_EVENT(cxl_port_aer_correctable_error,
>> + TP_PROTO(struct device *dev, u32 status),
>> + TP_ARGS(dev, status),
>> + TP_STRUCT__entry(
>> + __string(devname, dev_name(dev))
>> + __string(parent, dev_name(dev->parent))
>> + __field(u32, status)
>> + ),
>> + TP_fast_assign(
>> + __assign_str(devname);
>> + __assign_str(parent);
>> + __entry->status = status;
>> + ),
>> + TP_printk("device=%s parent=%s status='%s'",
>> + __get_str(devname), __get_str(parent),
>> + show_ce_errs(__entry->status)
>> + )
>> +);
>> +
>> TRACE_EVENT(cxl_aer_correctable_error,
>> TP_PROTO(const struct cxl_memdev *cxlmd, u32 status),
>> TP_ARGS(cxlmd, status),
>
>