From: Sohil Mehta <sohil.mehta@intel.com>
To: x86@kernel.org, Dave Hansen <dave.hansen@linux.intel.com>,
Tony Luck <tony.luck@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Namhyung Kim <namhyung@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@kernel.org>, Ian Rogers <irogers@google.com>,
Adrian Hunter <adrian.hunter@intel.com>,
Kan Liang <kan.liang@linux.intel.com>,
Thomas Gleixner <tglx@linutronix.de>,
Borislav Petkov <bp@alien8.de>, "H . Peter Anvin" <hpa@zytor.com>,
"Rafael J . Wysocki" <rafael@kernel.org>,
Len Brown <lenb@kernel.org>, Andy Lutomirski <luto@kernel.org>,
Viresh Kumar <viresh.kumar@linaro.org>,
Fenghua Yu <fenghua.yu@intel.com>,
Jean Delvare <jdelvare@suse.com>,
Guenter Roeck <linux@roeck-us.net>,
Zhang Rui <rui.zhang@intel.com>,
Andrew Cooper <andrew.cooper3@citrix.com>,
David Laight <david.laight.linux@gmail.com>,
Sohil Mehta <sohil.mehta@intel.com>,
linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-acpi@vger.kernel.org, linux-pm@vger.kernel.org,
linux-hwmon@vger.kernel.org
Subject: [PATCH v2 16/17] perf/x86: Simplify P6 PMU initialization
Date: Tue, 11 Feb 2025 19:44:06 +0000 [thread overview]
Message-ID: <20250211194407.2577252-17-sohil.mehta@intel.com> (raw)
In-Reply-To: <20250211194407.2577252-1-sohil.mehta@intel.com>
A switch case is unnecessary when only a single case matters. Also, the
gaps in the case numbers are due to no CPU with those model numbers
being released.
Avoid the switch case and combine the cases into simpler VFM checks.
Also, this gets rid of one last few Intel x86_model comparisons.
No functional change intended.
Signed-off-by: Sohil Mehta <sohil.mehta@intel.com>
---
v2: No change.
---
arch/x86/events/intel/p6.c | 28 +++++++---------------------
1 file changed, 7 insertions(+), 21 deletions(-)
diff --git a/arch/x86/events/intel/p6.c b/arch/x86/events/intel/p6.c
index a6cffb4f4ef5..37e3beb6d633 100644
--- a/arch/x86/events/intel/p6.c
+++ b/arch/x86/events/intel/p6.c
@@ -2,6 +2,8 @@
#include <linux/perf_event.h>
#include <linux/types.h>
+#include <asm/cpu_device_id.h>
+
#include "../perf_event.h"
/*
@@ -244,35 +246,19 @@ static __init void p6_pmu_rdpmc_quirk(void)
}
}
+/* Only called for Family 6 CPUs without X86_FEATURE_ARCH_PERFMON */
__init int p6_pmu_init(void)
{
x86_pmu = p6_pmu;
- switch (boot_cpu_data.x86_model) {
- case 1: /* Pentium Pro */
- x86_add_quirk(p6_pmu_rdpmc_quirk);
- break;
-
- case 3: /* Pentium II - Klamath */
- case 5: /* Pentium II - Deschutes */
- case 6: /* Pentium II - Mendocino */
- break;
-
- case 7: /* Pentium III - Katmai */
- case 8: /* Pentium III - Coppermine */
- case 10: /* Pentium III Xeon */
- case 11: /* Pentium III - Tualatin */
- break;
-
- case 9: /* Pentium M - Banias */
- case 13: /* Pentium M - Dothan */
- break;
-
- default:
+ if (boot_cpu_data.x86_vfm >= INTEL_CORE_YONAH) {
pr_cont("unsupported p6 CPU model %d ", boot_cpu_data.x86_model);
return -ENODEV;
}
+ if (boot_cpu_data.x86_vfm == INTEL_PENTIUM_PRO)
+ x86_add_quirk(p6_pmu_rdpmc_quirk);
+
memcpy(hw_cache_event_ids, p6_hw_cache_event_ids,
sizeof(hw_cache_event_ids));
--
2.43.0
next prev parent reply other threads:[~2025-02-11 19:46 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-11 19:43 [PATCH v2 00/17] Prepare for new Intel Family numbers Sohil Mehta
2025-02-11 19:43 ` [PATCH v2 01/17] x86/smpboot: Remove confusing quirk usage in INIT delay Sohil Mehta
2025-02-11 19:43 ` [PATCH v2 02/17] x86/smpboot: Fix INIT delay optimization for extended Intel Families Sohil Mehta
2025-02-11 20:10 ` Dave Hansen
2025-02-11 20:20 ` Sohil Mehta
2025-02-11 19:43 ` [PATCH v2 03/17] x86/apic: Fix 32-bit APIC initialization " Sohil Mehta
2025-02-11 19:43 ` [PATCH v2 04/17] x86/cpu/intel: Fix the movsl alignment preference for extended Families Sohil Mehta
2025-02-11 20:26 ` Dave Hansen
2025-02-11 21:45 ` David Laight
2025-02-11 19:43 ` [PATCH v2 05/17] x86/cpu/intel: Fix page copy performance " Sohil Mehta
2025-02-11 20:53 ` Dave Hansen
2025-02-12 0:54 ` Andrew Cooper
2025-02-12 21:19 ` Sohil Mehta
2025-02-13 23:02 ` Andrew Cooper
2025-02-14 0:29 ` Sohil Mehta
2025-02-11 19:43 ` [PATCH v2 06/17] cpufreq: Fix the efficient idle check for Intel " Sohil Mehta
2025-02-12 5:35 ` Zhang, Rui
2025-02-13 18:49 ` Sohil Mehta
2025-02-14 2:03 ` Zhang, Rui
2025-02-11 19:43 ` [PATCH v2 07/17] hwmon: Fix Intel Family-model checks to include " Sohil Mehta
2025-02-11 20:58 ` Dave Hansen
2025-02-11 21:38 ` Sohil Mehta
2025-02-12 13:43 ` Zhang, Rui
2025-02-12 16:57 ` Dave Hansen
2025-02-14 2:23 ` Zhang, Rui
2025-02-12 13:10 ` Zhang, Rui
2025-02-11 19:43 ` [PATCH v2 08/17] x86/microcode: Update the Intel processor flag scan check Sohil Mehta
2025-02-11 21:00 ` Dave Hansen
2025-02-11 19:43 ` [PATCH v2 09/17] x86/mtrr: Modify a x86_model check to an Intel VFM check Sohil Mehta
2025-02-11 21:00 ` Dave Hansen
2025-02-11 19:44 ` [PATCH v2 10/17] x86/cpu/intel: Replace early Family 6 checks with VFM ones Sohil Mehta
2025-02-11 21:03 ` Dave Hansen
2025-02-11 19:44 ` [PATCH v2 11/17] x86/cpu/intel: Replace Family 15 " Sohil Mehta
2025-02-11 21:03 ` Dave Hansen
2025-02-11 19:44 ` [PATCH v2 12/17] x86/cpu/intel: Replace Family 5 model " Sohil Mehta
2025-02-11 21:06 ` Dave Hansen
2025-02-11 19:44 ` [PATCH v2 13/17] x86/pat: Replace Intel x86_model " Sohil Mehta
2025-02-11 21:09 ` Dave Hansen
2025-02-11 21:42 ` Sohil Mehta
2025-02-11 19:44 ` [PATCH v2 14/17] x86/acpi/cstate: Improve Intel Family model checks Sohil Mehta
2025-02-11 21:20 ` Dave Hansen
2025-02-11 19:44 ` [PATCH v2 15/17] x86/cpu/intel: Bound the non-architectural constant_tsc " Sohil Mehta
2025-02-11 21:41 ` Dave Hansen
2025-02-12 0:45 ` Sohil Mehta
2025-02-11 19:44 ` Sohil Mehta [this message]
2025-02-11 19:44 ` [PATCH v2 17/17] perf/x86/p4: Replace Pentium 4 model checks with VFM ones Sohil Mehta
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