From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from frasgout.his.huawei.com (frasgout.his.huawei.com [185.176.79.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E5370264A8C; Fri, 14 Feb 2025 15:19:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.176.79.56 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739546384; cv=none; b=m+UG+482OEbRaVOVHsoSMbfUGPzSTW5Zfr17foZ63Rs8e04cwi7gzTwc3EriQgxKahCTCSCJ9ppkgH5gi5HmMbVym+ZtbSNAAxJlIq8Z9gUK9ztH7dVva9APD/X7Y0pf1LiWpaacirAjBuQk1o5DW1qgzVArqNf5IFtRWCa1wF0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739546384; c=relaxed/simple; bh=/+Uypwuv2xZI1+wUZnUWshSSnI7EG4nBKX740GUdeOs=; h=Date:From:To:CC:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=hcazD56INaTuHkX87S4S9Ol5xfnq/Piwxwgzw5Cvl/oSnTpEL3kLl2++fncB3V4NEpXARyLDVVkCBff/n5A6OPTQ4f5MUhy0Cjim8h6o3x3KPYrdHt95BoB+nQ1+eLQDvQcVnxaLHM4VCVH1xWdUEj7vv0QS2f2fTrftU0NXvLM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=185.176.79.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.18.186.231]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4YvbKP47n2z6HJfh; Fri, 14 Feb 2025 23:18:17 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id 35EAB140B38; Fri, 14 Feb 2025 23:19:39 +0800 (CST) Received: from localhost (10.203.177.66) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Fri, 14 Feb 2025 16:19:38 +0100 Date: Fri, 14 Feb 2025 15:19:36 +0000 From: Jonathan Cameron To: Terry Bowman CC: , , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v7 09/17] cxl/pci: Update RAS handler interfaces to also support CXL PCIe Ports Message-ID: <20250214151936.00007e23@huawei.com> In-Reply-To: <20250211192444.2292833-10-terry.bowman@amd.com> References: <20250211192444.2292833-1-terry.bowman@amd.com> <20250211192444.2292833-10-terry.bowman@amd.com> X-Mailer: Claws Mail 4.3.0 (GTK 3.24.42; x86_64-w64-mingw32) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: lhrpeml100004.china.huawei.com (7.191.162.219) To frapeml500008.china.huawei.com (7.182.85.71) On Tue, 11 Feb 2025 13:24:36 -0600 Terry Bowman wrote: > CXL PCIe Port Protocol Error handling support will be added to the > CXL drivers in the future. In preparation, rename the existing > interfaces to support handling all CXL PCIe Port Protocol Errors. > > The driver's RAS support functions currently rely on a 'struct > cxl_dev_state' type parameter, which is not available for CXL Port > devices. However, since the same CXL RAS capability structure is > needed across most CXL components and devices, a common handling > approach should be adopted. > > To accommodate this, update the __cxl_handle_cor_ras() and > __cxl_handle_ras() functions to use a `struct device` instead of > `struct cxl_dev_state`. > > No functional changes are introduced. > > [1] CXL 3.1 Spec, 8.2.4 CXL.cache and CXL.mem Registers > > Signed-off-by: Terry Bowman > Reviewed-by: Alejandro Lucero > Reviewed-by: Ira Weiny > Reviewed-by: Gregory Price Seems fine to me as well. Reviewed-by: Jonathan Cameron