Re: [PATCH v3 03/18] cxl/pci: cxl_hdm_decode_init: Move comment

Robert Richter
2025-03-06T09:38:26Z

On 14.02.25 15:49:55, Jonathan Cameron wrote:
> On Thu, 13 Feb 2025 01:35:29 +0100
> Robert Richter <rrichter@amd.com> wrote:
> > On 12.02.25 18:09:10, Jonathan Cameron wrote:
> > > On Tue, 11 Feb 2025 10:53:33 +0100
> > > Robert Richter <rrichter@amd.com> wrote:

> > > > + /*
> > > > + * Per CXL 2.0 Section 8.1.3.8.3 and 8.1.3.8.4 DVSEC CXL Range 1 Base
> > > > + * [High,Low] when HDM operation is enabled the range register values
> > > > + * are ignored by the device, but the spec also recommends matching the
> > > > + * DVSEC Range 1,2 to HDM Decoder Range 0,1. So, non-zero info->ranges
> > > > + * are expected even though Linux does not require or maintain that
> > > > + * match. If at least one DVSEC range is enabled and allowed, skip HDM
> > > > + * Decoder Capability Enable.
> > >
> > > This check is about mem_enabled. Would be fine to add another comment here to
> > > say.
> >
> > The next patch extends the comment for more clarification (I hope so).
>
> Not to me. It says 'else' when referring to what happens in the if.

I have dropped this patch and updated the comments in the next patch
along with the patch description.

-Robert