From: Yazen Ghannam <yazen.ghannam@amd.com>
To: "Zhuo, Qiuxu" <qiuxu.zhuo@intel.com>
Cc: "x86@kernel.org" <x86@kernel.org>,
"Luck, Tony" <tony.luck@intel.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>,
"Smita.KoralahalliChannabasappa@amd.com"
<Smita.KoralahalliChannabasappa@amd.com>
Subject: Re: [PATCH v2 08/16] x86/mce: Define BSP-only SMCA init
Date: Wed, 19 Feb 2025 11:01:29 -0500 [thread overview]
Message-ID: <20250219160129.GC337534@yaz-khff2.amd.com> (raw)
In-Reply-To: <CY8PR11MB7134F491D46892FD5669E3C589FA2@CY8PR11MB7134.namprd11.prod.outlook.com>
On Tue, Feb 18, 2025 at 03:33:08AM +0000, Zhuo, Qiuxu wrote:
> > From: Yazen Ghannam <yazen.ghannam@amd.com>
> > Sent: Friday, February 14, 2025 12:46 AM
> > To: x86@kernel.org; Luck, Tony <tony.luck@intel.com>
> > Cc: linux-kernel@vger.kernel.org; linux-edac@vger.kernel.org;
> > Smita.KoralahalliChannabasappa@amd.com; Yazen Ghannam
> > <yazen.ghannam@amd.com>
> > Subject: [PATCH v2 08/16] x86/mce: Define BSP-only SMCA init
> >
> > Currently on AMD systems, MCA interrupt handler functions are set during
> > CPU init. However, the functions only need to be set once for the whole
> > system.
> >
> > Assign the handlers only during BSP init. Do so only for SMCA systems to
> > maintain the old behavior for legacy systems.
>
> Looks like the interrupt handler is still set during each per-CPU online, right?
> What's the benefit/purpose of this patch? Thanks!
>
This patch is doing the "correct" thing.
> mce_cpu_online(cpu)
> mce_threshold_create_device(cpu) {
> ...
> mce_threshold_vector = amd_threshold_interrupt;
> ...
> }
>
This part remains for legacy systems. However, I think this is another
place to do more cleanup later.
Thanks,
Yazen
next prev parent reply other threads:[~2025-02-19 16:01 UTC|newest]
Thread overview: 63+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-13 16:45 [PATCH v2 00/16] AMD MCA interrupts rework Yazen Ghannam
2025-02-13 16:45 ` [PATCH v2 01/16] x86/mce: Don't remove sysfs if thresholding sysfs init fails Yazen Ghannam
2025-02-17 6:58 ` Zhuo, Qiuxu
2025-02-13 16:45 ` [PATCH v2 02/16] x86/mce/amd: Remove return value for mce_threshold_create_device() Yazen Ghannam
2025-02-17 7:11 ` Zhuo, Qiuxu
2025-02-17 14:09 ` Yazen Ghannam
2025-02-13 16:45 ` [PATCH v2 03/16] x86/mce/amd: Remove smca_banks_map Yazen Ghannam
2025-02-17 7:57 ` Zhuo, Qiuxu
2025-02-17 14:17 ` Yazen Ghannam
2025-02-13 16:45 ` [PATCH v2 04/16] x86/mce/amd: Put list_head in threshold_bank Yazen Ghannam
2025-02-18 1:28 ` Zhuo, Qiuxu
2025-02-13 16:45 ` [PATCH v2 05/16] x86/mce: Cleanup bank processing on init Yazen Ghannam
2025-02-13 22:32 ` Luck, Tony
2025-02-17 13:55 ` Yazen Ghannam
2025-02-18 16:40 ` Luck, Tony
2025-02-18 2:15 ` Zhuo, Qiuxu
2025-02-13 16:45 ` [PATCH v2 06/16] x86/mce: Remove __mcheck_cpu_init_early() Yazen Ghannam
2025-02-18 3:00 ` Zhuo, Qiuxu
2025-02-19 15:53 ` Yazen Ghannam
2025-02-27 15:25 ` Borislav Petkov
2025-02-27 16:31 ` Yazen Ghannam
2025-02-27 19:33 ` Borislav Petkov
2025-02-27 19:59 ` Yazen Ghannam
2025-02-27 20:48 ` Borislav Petkov
2025-02-28 14:29 ` Yazen Ghannam
2025-02-13 16:45 ` [PATCH v2 07/16] x86/mce: Define BSP-only init Yazen Ghannam
2025-02-18 3:16 ` Zhuo, Qiuxu
2025-02-19 15:57 ` Yazen Ghannam
2025-02-20 1:37 ` Zhuo, Qiuxu
2025-02-20 14:36 ` Yazen Ghannam
2025-02-24 13:28 ` Zhuo, Qiuxu
2025-02-13 16:45 ` [PATCH v2 08/16] x86/mce: Define BSP-only SMCA init Yazen Ghannam
2025-02-18 3:33 ` Zhuo, Qiuxu
2025-02-19 16:01 ` Yazen Ghannam [this message]
2025-02-13 16:45 ` [PATCH v2 09/16] x86/mce: Do 'UNKNOWN' vendor check early Yazen Ghannam
2025-02-18 5:31 ` Zhuo, Qiuxu
2025-02-13 16:45 ` [PATCH v2 10/16] x86/mce: Separate global and per-CPU quirks Yazen Ghannam
2025-02-18 6:03 ` Zhuo, Qiuxu
2025-02-19 16:06 ` Yazen Ghannam
2025-02-20 1:27 ` Zhuo, Qiuxu
2025-02-20 14:37 ` Yazen Ghannam
2025-02-13 16:46 ` [PATCH v2 11/16] x86/mce: Move machine_check_poll() status checks to helper functions Yazen Ghannam
2025-02-18 6:29 ` Zhuo, Qiuxu
2025-02-13 16:46 ` [PATCH v2 12/16] x86/mce: Unify AMD THR handler with MCA Polling Yazen Ghannam
2025-02-18 6:42 ` Zhuo, Qiuxu
2025-02-19 16:07 ` Yazen Ghannam
2025-02-13 16:46 ` [PATCH v2 13/16] x86/mce: Unify AMD DFR " Yazen Ghannam
2025-02-18 7:37 ` Zhuo, Qiuxu
2025-02-19 16:09 ` Yazen Ghannam
2025-02-20 1:41 ` Zhuo, Qiuxu
2025-02-20 14:41 ` Yazen Ghannam
2025-02-24 13:31 ` Zhuo, Qiuxu
2025-02-13 16:46 ` [PATCH v2 14/16] x86/mce/amd: Enable interrupt vectors once per-CPU on SMCA systems Yazen Ghannam
2025-02-18 8:23 ` Zhuo, Qiuxu
2025-02-19 16:16 ` Yazen Ghannam
2025-02-13 16:46 ` [PATCH v2 15/16] x86/mce/amd: Support SMCA Corrected Error Interrupt Yazen Ghannam
2025-02-13 22:34 ` Luck, Tony
2025-02-17 14:06 ` Yazen Ghannam
2025-02-18 13:27 ` Zhuo, Qiuxu
2025-02-19 16:19 ` Yazen Ghannam
2025-02-13 16:46 ` [PATCH v2 16/16] x86/mce: Handle AMD threshold interrupt storms Yazen Ghannam
2025-02-18 13:51 ` Zhuo, Qiuxu
2025-02-13 22:40 ` [PATCH v2 00/16] AMD MCA interrupts rework Luck, Tony
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250219160129.GC337534@yaz-khff2.amd.com \
--to=yazen.ghannam@amd.com \
--cc=Smita.KoralahalliChannabasappa@amd.com \
--cc=linux-edac@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=qiuxu.zhuo@intel.com \
--cc=tony.luck@intel.com \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox