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From: Yazen Ghannam <yazen.ghannam@amd.com>
To: "Zhuo, Qiuxu" <qiuxu.zhuo@intel.com>
Cc: "x86@kernel.org" <x86@kernel.org>,
	"Luck, Tony" <tony.luck@intel.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>,
	"Smita.KoralahalliChannabasappa@amd.com"
	<Smita.KoralahalliChannabasappa@amd.com>
Subject: Re: [PATCH v2 13/16] x86/mce: Unify AMD DFR handler with MCA Polling
Date: Wed, 19 Feb 2025 11:09:30 -0500	[thread overview]
Message-ID: <20250219160930.GF337534@yaz-khff2.amd.com> (raw)
In-Reply-To: <CY8PR11MB7134EE8E03532382B8FC23F389FA2@CY8PR11MB7134.namprd11.prod.outlook.com>

On Tue, Feb 18, 2025 at 07:37:18AM +0000, Zhuo, Qiuxu wrote:
> > From: Yazen Ghannam <yazen.ghannam@amd.com>
> > [...]
> > +static bool smca_should_log_poll_error(enum mcp_flags flags, struct
> > +mce_hw_err *err) {
> > +	struct mce *m = &err->m;
> > +
> > +	/*
> > +	 * If this is a deferred error found in MCA_STATUS, then clear
> > +	 * the redundant data from the MCA_DESTAT register.
> > +	 */
> > +	if (m->status & MCI_STATUS_VAL) {
> > +		if (m->status & MCI_STATUS_DEFERRED)
> > +			mce_wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(m-
> > >bank), 0);
> > +
> > +		return true;
> > +	}
> > +
> > +	/*
> > +	 * If the MCA_DESTAT register has valid data, then use
> > +	 * it as the status register.
> > +	 */
> > +	m->status = mce_rdmsrl(MSR_AMD64_SMCA_MCx_DESTAT(m-
> > >bank));
> > +
> > +	if (!(m->status & MCI_STATUS_VAL))
> > +		return false;
> > +
> > +	/*
> > +	 * Gather all relevant data now and log the record before clearing
> > +	 * the deferred status register. This avoids needing to go back to
> > +	 * the polling function for these actions.
> > +	 */
> > +	mce_read_aux(err, m->bank);
> > +
> > +	if (m->status & MCI_STATUS_ADDRV)
> > +		m->addr =
> > mce_rdmsrl(MSR_AMD64_SMCA_MCx_DEADDR(m->bank));
> > +
> > +	smca_extract_err_addr(m);
> > +	m->severity = mce_severity(m, NULL, NULL, false);
> > +
> 
> Is the following check in machine_check_poll() needed before 
> queuing/logging AMD's deferred error?
> 
>        if (mca_cfg.dont_log_ce && !mce_usable_address(m))
>              //Just clear MCA_STATUS, but not queue/log errors.
> 

Good question. Deferred errors are uncorrectable errors that don't need
immediate action. They are not correctable errors, so the 'dont_log_ce'
flag shouldn't apply.

Thanks,
Yazen

  reply	other threads:[~2025-02-19 16:09 UTC|newest]

Thread overview: 63+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-13 16:45 [PATCH v2 00/16] AMD MCA interrupts rework Yazen Ghannam
2025-02-13 16:45 ` [PATCH v2 01/16] x86/mce: Don't remove sysfs if thresholding sysfs init fails Yazen Ghannam
2025-02-17  6:58   ` Zhuo, Qiuxu
2025-02-13 16:45 ` [PATCH v2 02/16] x86/mce/amd: Remove return value for mce_threshold_create_device() Yazen Ghannam
2025-02-17  7:11   ` Zhuo, Qiuxu
2025-02-17 14:09     ` Yazen Ghannam
2025-02-13 16:45 ` [PATCH v2 03/16] x86/mce/amd: Remove smca_banks_map Yazen Ghannam
2025-02-17  7:57   ` Zhuo, Qiuxu
2025-02-17 14:17     ` Yazen Ghannam
2025-02-13 16:45 ` [PATCH v2 04/16] x86/mce/amd: Put list_head in threshold_bank Yazen Ghannam
2025-02-18  1:28   ` Zhuo, Qiuxu
2025-02-13 16:45 ` [PATCH v2 05/16] x86/mce: Cleanup bank processing on init Yazen Ghannam
2025-02-13 22:32   ` Luck, Tony
2025-02-17 13:55     ` Yazen Ghannam
2025-02-18 16:40       ` Luck, Tony
2025-02-18  2:15   ` Zhuo, Qiuxu
2025-02-13 16:45 ` [PATCH v2 06/16] x86/mce: Remove __mcheck_cpu_init_early() Yazen Ghannam
2025-02-18  3:00   ` Zhuo, Qiuxu
2025-02-19 15:53     ` Yazen Ghannam
2025-02-27 15:25   ` Borislav Petkov
2025-02-27 16:31     ` Yazen Ghannam
2025-02-27 19:33       ` Borislav Petkov
2025-02-27 19:59         ` Yazen Ghannam
2025-02-27 20:48           ` Borislav Petkov
2025-02-28 14:29             ` Yazen Ghannam
2025-02-13 16:45 ` [PATCH v2 07/16] x86/mce: Define BSP-only init Yazen Ghannam
2025-02-18  3:16   ` Zhuo, Qiuxu
2025-02-19 15:57     ` Yazen Ghannam
2025-02-20  1:37       ` Zhuo, Qiuxu
2025-02-20 14:36         ` Yazen Ghannam
2025-02-24 13:28           ` Zhuo, Qiuxu
2025-02-13 16:45 ` [PATCH v2 08/16] x86/mce: Define BSP-only SMCA init Yazen Ghannam
2025-02-18  3:33   ` Zhuo, Qiuxu
2025-02-19 16:01     ` Yazen Ghannam
2025-02-13 16:45 ` [PATCH v2 09/16] x86/mce: Do 'UNKNOWN' vendor check early Yazen Ghannam
2025-02-18  5:31   ` Zhuo, Qiuxu
2025-02-13 16:45 ` [PATCH v2 10/16] x86/mce: Separate global and per-CPU quirks Yazen Ghannam
2025-02-18  6:03   ` Zhuo, Qiuxu
2025-02-19 16:06     ` Yazen Ghannam
2025-02-20  1:27       ` Zhuo, Qiuxu
2025-02-20 14:37         ` Yazen Ghannam
2025-02-13 16:46 ` [PATCH v2 11/16] x86/mce: Move machine_check_poll() status checks to helper functions Yazen Ghannam
2025-02-18  6:29   ` Zhuo, Qiuxu
2025-02-13 16:46 ` [PATCH v2 12/16] x86/mce: Unify AMD THR handler with MCA Polling Yazen Ghannam
2025-02-18  6:42   ` Zhuo, Qiuxu
2025-02-19 16:07     ` Yazen Ghannam
2025-02-13 16:46 ` [PATCH v2 13/16] x86/mce: Unify AMD DFR " Yazen Ghannam
2025-02-18  7:37   ` Zhuo, Qiuxu
2025-02-19 16:09     ` Yazen Ghannam [this message]
2025-02-20  1:41       ` Zhuo, Qiuxu
2025-02-20 14:41         ` Yazen Ghannam
2025-02-24 13:31           ` Zhuo, Qiuxu
2025-02-13 16:46 ` [PATCH v2 14/16] x86/mce/amd: Enable interrupt vectors once per-CPU on SMCA systems Yazen Ghannam
2025-02-18  8:23   ` Zhuo, Qiuxu
2025-02-19 16:16     ` Yazen Ghannam
2025-02-13 16:46 ` [PATCH v2 15/16] x86/mce/amd: Support SMCA Corrected Error Interrupt Yazen Ghannam
2025-02-13 22:34   ` Luck, Tony
2025-02-17 14:06     ` Yazen Ghannam
2025-02-18 13:27   ` Zhuo, Qiuxu
2025-02-19 16:19     ` Yazen Ghannam
2025-02-13 16:46 ` [PATCH v2 16/16] x86/mce: Handle AMD threshold interrupt storms Yazen Ghannam
2025-02-18 13:51   ` Zhuo, Qiuxu
2025-02-13 22:40 ` [PATCH v2 00/16] AMD MCA interrupts rework Luck, Tony

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